A Low-Voltage Current Mirror for Transconductance Amplifiers Nizkonapetostno tokovno zrcalo za transkonduktančne ojačevalnike

: In this study, a low-voltage current mirror to use in differential pairs as an active load is introduced. The proposed current mirror which can operate at ±0.5 V has high output impedance and low input impedance. The proposed structure employs the principle of voltage level-shifting for PMOS transistors. The voltage level-shifting operation has been achieved by using the bulk voltage at this structure. Spice simulations also justify this current mirror’s outstanding performance with a bandwidth of 11 GHz using an external capacitor at an input current of 200 μA.


Introduction
Nowadays, integrated circuit design has concentrated on a circuit with low-voltage operation, low-power dissipation, wide bandwidth and minimum area requirements. A growing need has emerged associated with low-voltage analog circuit design. The demand for circuits operating at low voltage has increased due to the need for low power dissipation. The low-voltage and low-power designs have increased operation time between the battery recharging cycle and have utilized a smaller or lighter-weight battery. Numerous low voltage applications have been proposed earlier [1,2]. Considering several technologies such as bipolar junction transistor (BJT), metal-oxide-semiconductor (MOS) and bipolar complementary MOS (BiCMOS), the CMOS technology has played a crucial role in the development of low power circuit for diverse applications.
The current mirror has been known as a circuit having two terminals whose output current is independent of the output voltage and depends only on the input current. These circuits copying the current carry out a significant function for active elements such as Op-Amp, OTA, current conveyor etc. The low-voltage current mirror has been used in a lot of active elements designed with low-power. The performance parameters of current mirrors like active elements parameters contain linearity, power dissipation, minimum supply voltage requirement, input and output resistance in these applications. At the same time, many active elements include differential pairs designed using PMOS current mirror as an active load [3][4][5][6]. The low-voltage operation of the active elements has been restricted because these current mirrors have high input voltage. A low voltage level shifter-based current mirror has been presented in Ref. [7] for current sensor application. Ac-cording to this study, the bandwidth of the circuit was a few tens of MHz. Though this current mirror can be used in low voltage design, the level shifter approach has been designed using only the NMOS current mirror. The threshold voltage of the PMOS transistor is always higher than that of the NMOS. Thus, the circuit presented in Ref. [7] cannot be obtained using a PMOS transistor. However, this case has been resolved by using the proposed circuit.
In the present study, a low-voltage PMOS current mirror employing voltage level-shifting principle has been introduced. The voltage level-shifting operation has been achieved by using bulk voltage in this structure. The circuit utilizes a voltage level shifter at the input port to achieve the high input voltage swing capability. Thus, it can operate with low power supply voltage and low input /low output voltage requirements. Additionally, the proposed structure as an active load has been used in the transconductance amplifier.

Conventional PMOS current mirror
A conventional PMOS current mirror (CM) circuit is shown in Figure 1. Transistor M 1 has been used as a diode and the input current copied to output has been compelled to pump by the input voltage. Transistor M 1 shown in Figure 1, operates in saturation mode. Besides, the input impedance of the CM depends on the transconductance (g m ) of the M 1 . The input voltage of the circuit can be written as below: where k p =µ p C ox is the conduction factor, V THP is the threshold voltage for PMOS transistor, V DD represents the supply voltage. Also, W and L are the effective transistor width and length. The output voltage requirement of the CM can be given as where V DS,sat is drain-to-source voltage for relevant transistors in the saturation region. One of the drawbacks of the conventional PMOS CM is that input voltage is always greater than the threshold voltage, being a crucial parameter for low-voltage application. The other disadvantage is the low output impedance. Therefore, using this structure is inconvenient in the low voltage. By using the proposed approach, these challenges have been met.  Threshold voltage can be defined by [11] ( )

PMOS level-shifter current mirror
where V THN is the threshold voltage for M 3 , V THO is the zero-V BS value of the threshold voltage, ɸ F is the surface inversion potential of silicon, γ is the body effect parameter and V BS (V bulk -V S ) is the bulk-source voltage. V BS represents the bulk-source voltage for M 3 . As shown in Figure 2, transistor M 3 has been used for shifting the voltage level at the drain terminal of M 1 . The high value of the biasing current forces M 3 to operate in the saturation region. According to these results, the relation between the voltages can be written as below ( ) where V SG1 and V GS3 are the gate-to-source voltage of the relevant transistors. The equations describing the operation in saturation and sub-threshold regions, respectively are where I D1 and I D3 are the drain currents of transistors M 1 and M 3 , respectively. Besides, k p =µ n C ox is the transconductance parameter of the PMOS transistor, U T is the thermal voltage and I D03 is the saturation current. Also, I D03 and n are the process-dependent constants. From Equation (5), the V SG1 and V GS3 can be obtained as ( ) The input voltage of LSCM can be written as below by using Equations (5) and (6). For low voltage operation, V THN > |V THP | and I in > I b1 is required. This condition related to threshold voltages is arranged when the bulk-source voltage of the M3 is negative value using the bulk voltage (V bulk ) as shown in Equation (3).
The output voltage necessity for the proposed PMOS LSCM is given by

Proposed low-voltage PMOS current mirror structure
The low-voltage PMOS current mirror (LVCM) structure is shown in Figure 3. The input voltage for the proposed CM is given by From Equation (3), it can be seen that the threshold voltage can be increased by using the bulk-source voltage for M 3 and M 6 . Hence, it should be indicated that this condition for the PMOS transistor can achieve levelshifting operation. If Figure 3 is analyzed, it can be seen that V SG1 > V GS3 and V SG4 > V GS6 because there is a relationship between voltages as V THN > V THP . This condition is arranged when the bulk-source voltage of the M 5 and M 6 is negative value as seen in Equation (3). Also, the input voltage of the CM shown in Figure 3 can be written as ( ) where k p =µ n C ox is the transconductance parameter of the PMOS transistor, U T is the thermal voltage and I D03 , I D06 is the saturation current. Also, I D03 , I D06 and n are the process-dependent constants. The maximum output voltage requirement for the proposed CM is given by Input and output impedances of the proposed circuit can be defined as  If the M 3 and M 6 are considered identical, the biasing current I b1 can be given as I D07 is the saturation current. Also, I D07 and n are the process-dependent constants. I b2 can be defined as similar to I b1 . It can be seen that these currents are always low. Thus, the M 3 and M 6 operate in the sub-threshold region. Also, using an external capacitance (C) shown in Figure 4 decreases effective input capacitance. Figure 5 (a) indicates the conventional transconductance amplifier circuit. Figure 5 (b) indicates the proposed transconductance amplifier circuit for use in low voltage applications.
The drain resistance as a load is used in the transconductance amplifier. Replacing the drain resistance with a current mirror as an active load results in much higher voltage gain [11]. The proposed LVCM as an active load can be used in the transconductance amplifier shown in Figure 5 (b). Transconductance can be expressed as Here, it can be determined as G m ≈ g m = g m9 = g m10 . Where V 1 , V 2 are the input voltages, I 0 is the output current, g m9 and g m10 are the transconductances of transistors M 9 and M 10 , respectively. W/L is the aspect ratio of the transistors using for differential pair. The bulk for differential pair is connected to drain in Figure 5 (b). Body bias is used to dynamically adjust the threshold voltage (V TH ) of a CMOS transistor. The polarity of the body bias for M 9 and M 10 is positive values. This situation causes a decrease in the value of V TH for M 9 and M 10 . The bulk-connected structure is suitable for low voltage applications. Also, the current I B is the biasing current for the differential pair. A low-voltage transconductance amplifier has been used in many active elements designed with low-power such as Op-Amp, OTA and current conveyor [1][2][3][4]. Thus, these active elements have gained operating capability at the low-voltage by using the proposed circuit.

Simulation results
The current mirror circuits (Figs. 1, 2, and 4) were simulated for TSMC 0.13 μm technology. The aspect ratios of the transistors are given in Table 1. All the circuit operations have been simulated for the supply voltage ±0.5 V. Currents I b1 and I b2 are selected as 20 nA. Also, V bulk is equal to -0.5V (V SS ). Comparison of current/voltage characteristics of the current mirrors is illustrated in Figure 6. V in is the input voltage for LVCM is shown in Figure 3. The value of V in is taken as 0 V. The I / V characteristic shown in Figure 6 is obtained by changing the supply voltage between 0 mV and 600 mV.
It is clearly shown that the supply voltage of the proposed LVCM requires the lowest value of the supply voltage compared to any other structures. Therefore, the proposed circuit is suitable for low voltage applications. The current transfer characteristic exhibits linear behavior as depicted in Figure 7. However, deviation from linearity occurs for larger value of currents.
The percentage gain error (I out / I in ) of the proposed circuit is approximately 0.3 % for I in =200 µA as displayed in Figure 8. Whereas, the percentage gain error (I out / I in ) of the PMOS LSCM and conventional CM are 0.6 % and 0.9 % for I in =200 µA, respectively.  is taken as 0 V (V out = 0 V). Considering the output current of the proposed LVCM it can be operated at 0.5 V as shown in Figure 9. The frequency responses of the current mirrors are indicated in Figure 10. There is an improvement in the bandwidth when a capacitance (C) is used and the bandwidth is found to be 11 GHz. It is shown that the bandwidth reduces to 5 GHz when the C is not used in the design. It is seen that as the capacity value increases, the bandwidth increases. Also, the capacitance (C) has a value of 100 pF. The bandwidth of the PMOS LSCM and conventional CM are 0.24 GHz and 17.2 GHz, respectively.
The capacitance (C) has a value of 100 pF for 11 GHz shown in Figure 11. As the capacitance value decreases, the bandwidth decreases. The bandwidth can be sacrificed to obtain the lower value of capacitance. The temperature effect on gain-bandwidth performance of the LVCM is depicted in Figure 12. The current gain is about equal to 0.35 dB for 75 °C as shown in Figure 12. Although higher temperature increases the gain of the LVCM the increase is tolerable. The LVCM exhibits temperature-dependent bandwidth characteristics depending on transistors M 3 and M 6 operates in sub-threshold region as shown in Figure 3. The Monte Carlo analysis which is repeated for 30 times is illustrated in Figure 13.   Figure 13 indicates the good performance of the proposed circuit versus mismatches.
Performance comparison of the aforementioned current mirrors is depicted in Table 2.  When the performance parameters of the CMs are investigated, it is clearly shown that the proposed structure has a lot of advantages compared with the others. Significantly, the proposed circuit's input resistance is much lower than the others, and it is seen that the suggested LVCM's low input voltage is one of the critical advantages. Also, the gain error belonging to currents (I out / I in ) of the proposed circuit is reasonable compared to the other circuits.
The low-voltage transconductance amplifier used the LVCM and the conventional transconductance amplifier is shown in Figure 5. These circuits were simulated for TSMC 0.13 μm technology. The aspect ratios of the transistors are given in Table 1.
The relation between input difference voltage and output current of the transconductance amplifiers is depicted in Figure 14. Also, the supply voltage has been chosen as ±0.5 V for both amplifiers. The value of I B shown in Figure 5 is chosen as 50 µA. Conventional transconductance amplifier has not exhibited good performance at low voltage. The circuit has not strictly operated at ±0.5 V for the negative values of the output current. It is shown that the proposed circuit is more suitable than the other circuit for low voltage applications. However, a conventional transconductance amplifier can only be operated on minimum supply voltage with ±0.65 V, while the proposed circuit can be employed for lower voltage.  As seen in Figure 15, the presented circuit consumes lower power than the conventional circuit for diverse biasing currents. The proposed circuit consumes 70 µW for 50 µA of biasing current. Hence, the suggested circuit is suitable for low-power applications.
The frequency performance of the transconductance amplifiers is illustrated in Figure 16. The total harmonic distortion (THD) is evaluated for input voltage with different amplitudes for a biasing current of 50 µA, as shown in Figure 17. The fundamental frequency (1st harmonic) has been specified and THD has been calculated via the PSpice program. The third harmonic provides the most important contribution to the total harmonic distortion of the circuit. The THD has a value of about 0.94% for 250 mV P-P . It is shown that THD obtained according to the different peak-to-peak input voltages are reasonable values.

Conclusion
A low-voltage current mirror circuit employing the voltage level-shifting principle is demonstrated for use in differential pair as an active load. The proposed current mirror operates at ±0.5 V and its bandwidth is about 11 GHz. Also, it consumes 56.6 µW power. The proposed circuit exhibits better performance than the other CMs called PMOS CM and level shifter CM. It is undeniable that the simulation results confirm the validity of the theory and demonstrate the usage of the LVCM in electronic applications. Also, the proposed transconductance amplifier using LVCM has been compared to the conventional one. The proposed transconductance amplifier's bandwidth is about 581.1 MHz. It consumes 70 µW power. Finally, such a current mirror is appropriate for low-voltage applications, resulting in increasing threshold voltage. Hereafter, the suggested PMOS current mirror would be operated even at lower supply voltages if the threshold voltages could be decreased.