Practical Floating Capacitance Multiplier Implementation with Commercially Available IC LT1228s Praktična uporaba množilnika plavajoče kapacitivnosti s komercialnim IC LT1228s

: A practical realization of a tunable floating capacitance multiplier using commercially available integrated circuits, namely LT1228 is proposed. The synthetic capacitor utilizes only two IC LT1228s along with two passive components (one resistor and one capacitor). The capacitance multiplication factor is electronically controllable through the transconductance gain of the LT1228. The effects of non-ideal transfer gains and parasitic elements of the LT1228 on the circuit performance have been evaluated in detail. The applicability of the proposed floating capacitance multiplier as a second-order band-pass filter is also presented. The claimed theory is verified by several PSPICE simulations and experimental test results.


Introduction
It is well known that the capacitance multiplier is a significant electronic block in the fabrication of high capacitance values in integrated circuit (IC) technology [1]- [2]. This is due to the large-value capacitors requiring a large silicon area on the IC chip. To overcome this limiting problem, the capacitance multiplier circuit which performs the multiplication of small capacitance values can be very useful [3]- [4]. Therefore, the design of capacitance multiplier circuits becomes an essential research issue in the area of analog ICs. Over the years, there are various floating capacitance multiplier circuits reported by several researchers employing numerous versatile active elements [5]- [13]. However, careful observation of the topologies reported in these references reveals that they still suffer from one or more of the following restrictions: 1.
The attention aim of this work is, therefore, to design a floating and tunable capacitance multiplier using already existing commercially available ICs, namely LT1228 [14]. The LT1228 structure internally consists of an operational transconductance amplifier (OTA) and a current feedback operational amplifier (CFOA) in the same IC package. Thus, it may be noted that LT1228 has now become a popular commercial IC for designing several types of analog signal processing circuits and applications [15]- [20]. Two LT1228s and two passive components, i.e. one resistor and one capacitor, are employed in this design. The capacitance scaling factor of the simulated circuit can be altered through the tunable transconductance gains of the LT1228s and/or the resistor in the circuit. A careful non-ideality analysis for the proposed capacitance multiplier circuit is investigated in detail. The second-order RLC band-pass filter implemented with the proposed tunable active capacitance simulator is given as an application. To verify the workability of the proposed circuit, it has been simulated in the PSPICE program using macro-model of IC LT1228, and also experimentally tested in a laboratory using commercially available IC namely LT1228s.

Circuit description 2.1 Commercially available IC LT1228
The LT1228 is a commercially available IC manufactured by Linear Technology Corporation [14]. The LT1228 internal circuit, which has the properties of both the operational transconductance amplifier (OTA) and the current feedback operational amplifier (CFOA), is shown in Fig.1(a). The OTA provides an electronic gain control with a differential voltage-to-current converter, whose transconductance gain (g m ) depends on an external bias current, while the CFOA is implemented to drive load low-impedance loads with excellent linearity at high frequencies. The circuit representation block of the LT1228 and its equivalent circuit are given in Fig.1(b) and 1(c), respectively. In ideal operation, the function of the LT1228 can be described by the following matrix relation: In equation (1), R OL is the transresistance gain of the LT1228, which is ideally considered to be infinite. The g m -parameter of this IC can be adaptable electronically with the help of the external bias current I B and the expression is given by:

Proposed floating capacitance multiplier design
The schematic diagram of the proposed floating capacitance multiplier circuit is given in Fig.2(a). It is composed of only two LT1228s, one resistor, and one capacitor. The equivalent circuit for the proposed capacitor implementation of Fig.2(a) is shown in Fig.2(b). Assuming that the matching condition of g m = g m1 = g m2 is satisfied, routing circuit analysis shows that the equivalent input impedance looking between ports v 1 and v 2 of the proposed circuit in Fig.2(a) can be obtained as: It is obvious that the proposed circuit of Fig.2(a) implements a floating tunable lossless capacitance with equivalent capacitance being given by: where K = g m R 1 represents the capacitance multiplication factor. The relation in (4) reveals that the capacitance magnification with a large multiplication factor is easily feasible by appropriate choosing g m and/or R 1 . Also from equation (2), the electronic tuning capability of the proposed design is evident through the bias currents of the LT1228s. It should be further noted here that two transconductance gains for this implementation need to be equal. This can be done easily by using simple current mirror to supply equal external bias currents to the two LT1228s.

Non-ideality performance analysis
Consider the non-ideal transfer gains of the LT1228, the characteristic of the LT1228 given in equation (1) can be re-described by the following matrix equation: In above equation, α = (1 -ε gm ) and β = (1 -ε v ), where |ε gm | << 1 and |ε v | << 1 are the transconductance tracking error and the voltage transfer error, respectively. Therefore, an analysis of the simulator given Fig.2(a) with the consideration of these parasitic gains gives the following expression for the equivalent input impedance looking into port 1 and ground as: It is obvious that the parasitic gains α 1 and β 1 directly deviate the value of the working capacitance C 1 . To compensate for this, it can be governed by tuning the appropriate value for the g m1 R 1 product. On the other hand, the non-ideal equivalent impedance looking into port 2 and ground can be approximately found as: From equation (7), due to the LT1228 non-ideal gains, there is an extra undesired parallel resistance (R ′ ex ) appearing in parallel with the non-ideal equivalent capacitance. The non-ideal equivalent circuit for this case can then be represented as in Fig.3, where C ′ eq2 = (R 1 C 1 β 2 )(g m2 α 2 ) and R ′ ex = 1/(β 2 -1)(g m2 α 2 ). Since a typical value of R ′ ex is of the order of hundreds of kΩ, the parasitic elements C ′ eq2 and R ′ ex introduce an extra pole at low frequency, which restricts the operating frequency range of the circuit. This effect on the frequency response of Z ′ eq2 will be shown in the following section. In practice, if the parasitic impedances at the corresponding LT1228 terminals are taken into account, then the practical circuit model of the LT1228 can be drawn in Fig.4. At terminals p, n and z, there are the parasitic resistances R p , R n , and R z appearing respectively in parallel with the parasitic capacitances C p , C n , and C z . Their impedance values are theoretically equal to infinity. On the other hand, the parasitic resistance R x appears in series at terminal x. By considering v 2 = 0, the impedance of the designed capacitor with the consideration of the parasitic element effects can be given by: where R OLi , R xi , R zi , and C zi (i = 1, 2) are the parasitic elements R OL , R x , R z , and C z of the i-th LT1228, respectively. For practical realization, R OL1 and R z1 are typically very large, yielding R OL1 >> R x1 and R z1 >> 1. Therefore, an equivalent capacitance C ″ eq1 ≅ (g m1 R 1 C 1 -C z1 ) is obtained from equation (8). It is further mentioned that there is not any additional parasitic pole and zero due to the parasitic elements, and the operating frequency limitation can be expressed as: By defining v 1 = 0 and conducting relevant analyses, we can obtain the following expression for the non-ideal impedance seen between terminal 2 and ground as: where R ″ 2 = R n1 //R p2 //R z2 and C ″ 2 = C n1 +C p2 +C z2 . In equation (9), the negative terms exhibit non-ideal behavior of the proposed capacitance simulator by introducing a parallel resistive effect. Since R OL2 >> R x2 and R ″ 2 >> 1, then equation (9) reduces to The consideration of the above effect implies that in the frequency range of f ≤ min [1/2π(g m2 R 1 C 1 -C ″ 2 )], and the inequality g m2 R 1 C 1 << C ″ 2 , the simulator operates practically as an expected ideal capacitance multiplier.

Computer simulation validation
To verify our proposed design, the circuit in Fig.2 (2), the transconductance gains are calculated as: g m = g m1 = g m2 = 2 mA/V. Also, from the relation in (4), the capacitance multiplication factor, and the simulated equivalent capacitance are calculated as: K = 2 and C eq = 0.1 nF, respectively. The simulation results for input signals v id and i in of the proposed capacitance multiplier are given in Fig.5, when a 1-MHz sinusoidal signal of an amplitude 50 mV (peak) was applied as an input signal. The phase difference between v id and i in was observed to be 86.77° leading, as against the theoretical value of 90°. The corresponding frequency responses are also given in Fig.6. The total power consumption is measured to be 0.12 W when v 1 and v 2 are kept grounded.  Fig.2(a).
In order to evaluate the impact of the unwanted parasitic resistance R ′ ex the frequency responses of the non-  Fig.7. It is observed that, at low frequency range between 1 kHz and 20 kHz, R ′ ex mainly causes drop of the magnitude response of the Z ′ eq2 and also some deviates in phase response as depicted. However, some circuit techniques which reduce the parasitic impedance effects can be applied in the proposed capacitance multiplier circuit to improve the frequency performance [21]- [23].   Fig.3.
The adjustability of the proposed capacitance multiplier circuit is assessed by tuning the capacitance multiplication factor (K = g m R 1 ), and also shown in Fig.8. Variations of C eq against g m and R 1 are demonstrated as examples. The C eq tuning with g m (varied from 0.1 mA/V to 10 mA/V) while keeping R 1 constant at 20 kΩ is shown in Fig.8(a), whereas the results in Fig.8(b) are obtained by setting g m fixed at 10 mA/V and varying R 1 from 0.5 kΩ to 20 kΩ. It is evident from the results that the simulated capacitance value C eq can enhance up to approximately 200 times with the maximum error in all cases less than 10%. Fig.9 shows the temperature analysis results of the proposed capacitance multiplier circuit in Fig.2(a), where the ambient temperature is changed from 0°C to 100°C in the step of 20°C. From Fig.9, the simulation results demonstrate that the magnitude response has deviated with a variation of -8% ∼ +22% over the temperature range of 0°C to 100°C.

Experimental Evaluation
In the experimental evaluation, the availability of the proposed floating capacitance multiplier circuit in  Fig.2(a) has been verified in the laboratory using offshelf IC's LT1228 [14] under ±5V supply voltages. All experimental measurements were performed through Keysight EDU-X 1002G oscilloscope and HP4395A impedance analyzer. To perform the experimental test, the components used have been: g m = 2 mA/V (I B = 200 µA), R 1 = 1 kΩ, and C 1 = 50 pF, yielding C eq = 0.1 nF. Fig.10 shows the measured input waveforms v id and i in of the proposed circuit in Fig.2(a), when the input signal is 100 mV peak-to-peak at 1 MHz. The phase shift between v id and i in obtained from this experiment is measured as 86.8°. The corresponding frequency responses of the equivalent input impedance Z eq are also represented in Fig.11. It appears from Figs.10 and 11 that the proposed circuit behaves as a lossless capacitor as expected.  Fig.2(a).
So as to survey the electronic tunability of the capacitance multiplier circuit, the measured magnitude and phase responses with three different values of g m (i.e. g m = 0.5 mA/V, 3 mA/V, and 5 mA/V) are shown in Fig.12. These results were obtained by taking R 1 = 1 kΩ and C 1 = 50 pF. This tuning process leads to obtain K = 0.5, 3 and 5 (C eq = 25 pF, 0.15 nF, and 0.25 nF), respectively.
On the other hand, the magnitude-frequency responses of Z eq for different values of R 1 are depicted in Fig.13. In Fig.13, setting g m = 1 mA/V and C 1 = 50 pF, and different values for R 1 as 5 kΩ, 10 kΩ and 20 kΩ, results in the theoretical equivalent capacitances of C eq = 0.25 nF, 0.5 nF, and 1 nF, respectively.

Illustrative application
In this section, illustrative applicability of the proposed floating capacitance multiplier given in Fig.2(a) has been considered. It may be utilized in the implementation of the second-order RLC voltage-mode band-pass (BP) filter as shown in Fig.14. The transfer function of the filter can be given by: The center frequency (ω c ) and the quality factor (Q) are respectively expressed below: As an example for the circuit simulation, the following passive and active components were chosen as: R BP = 3.3 kΩ, L BP = 1 mH, and C eq = 0.1 nF (g m = 2 mA/V, kΩ, and C 1 = 50 pF). The ideal and simulated frequency responses of the filter in Fig.14 are exhibited in Fig.15, in which the calculated and simulated values of f c are found to be 503 kHz and 509 kHz, respectively. The simulated frequency characteristics are in good agreement with the predicted responses, thereby confirming the practical utility of the proposed capacitance multiplier circuit. The corresponding frequency spectrum of the output voltage (v out ) of the BP filter is also recorded in Fig.16, where the total harmonic distortion (THD) values observed is well within 1.17%.   Finally, in order to inspect random deviations of the BP filter center frequency due to the process and mismatch variations, Monte-Carlo analysis simulation has been evaluated with the same given parameters that resulted in the frequency characteristic of Fig.15. The simulations were performed 200 times with a 5% Gaussian deviation of relevant g m , R 1 , and C 1 . The histogram of the center frequency is shown in Fig.17. According to statistical analysis results, the mean value is at 522 kHz with a standard deviation of 9.4 kHz, corresponding to 1.8% deviation from the nominal value.

Conclusive Discussion
This work is an attempt to present a practical realization of the tunable floating capacitance multiplier circuit using a commercially available IC LT1228. The synthetic capacitance simulator is constructed with two LT1228s, one resistor, and one capacitor. The electronic tuning feature of the simulated floating capacitor can be achieved by means of external bias currents of the IC LT1228s. The communication further discusses a second-order RLC voltage-mode band-pass filter to validate the applicability of the proposed capacitor simulation. PSPICE simulation and experimental results of the commercially available IC LT1228 are also included to demonstrate the convincing characteristics of the proposed circuit and its practical significance.