Simulation on the Interfacial Singular Stress-strain Induced Cracking of Microelectronic Chip Under Power On-off Cycles

: Thermal fatigue failure of a microelectronic chip usually initiates from the interface between the solder joint and substrate due to the mismatch in coefficients of thermal expansion (CTE). Because of the viscoelastic creep properties of the solders, the stress and strain at the solder/substrate interfaces are strongly dependent on temperature and time. Based on the established creep constitutive models of the solder materials, a three-dimensional thermomechanical analysis of the microelectronic chip undergoing power on-off cycles is conducted based on the finite element method (FEM). The singular interfacial stress-strain fields are obtained and the singular field parameters are quantitatively evaluated. Furthermore, the crack nucleation in power on-off fatigue test of the microelectronic chip is observed, to verify the conclusion that the singular stress-strain induces thermal fatigue failure from the solder/ substrate interface.


Introduction
The flip flat package technology is currently widely used in electronic engineering to meet the demands of high-speed functions and system miniaturization [1]. The high density and cost-effective requirements of the package structure have led to the emergence of small size and multiple input/output (IO) points in chip design. Solder joints, as the mechanical, electrical and heat-dissipating components, require excellent reliabilities during soldering and service [2][3]. In the soldering process, the formation of intermetallic compounds (IMCs) is a necessary condition for the forma-tion of solder joints, and the reliability of solder joints is highly dependent on the formation and growth of IMC at the interface [4]. With the growth of intermetallic compounds, stress concentration easily appears at the interface of solder joint due to the mismatch of coefficients of thermal expansion of the materials, which causes the cracking and reduces the service life of solder joints [5][6]. Due to the increase of packaging density, both the size and shape of solder joints appear in various combinations, a quantitative evaluation method of the strength and life for solder joints is strongly expected.
Under thermal cyclic loading, failure or fatigue crack generally initiates from the interface edge or near to the interface between the solder joint and substrate, and its mechanism is strongly affected by the stress singularity at the interface edge or stress concentration induced by the interface [7][8][9]. Therefore, it is of practical importance to determine the stress state at the interface, so that the susceptibility to thermomechanical failure can be predicted for new geometry-tomaterial combinations. The traditional strength-based methods are not suitable since the stresses are singular even at the idealized interface edges or corners [10][11][12]. To overcome this concern, Hattori et al. [13] have suggested a singularity parameter approach for the interface reliability of plastic IC packages using two stress intensity parameters that characterize the stress distribution near a bonded edge along with the interface. Other authors [14][15][16] argued that the two parameters: singular order λ and stress intensity factor K, can be used in a criterion for crack initiation or delamination for certain structure configurations. Generally, FEM is a valuable tool for determining the constants λ and K. At the same time, finite element modeling enables the design to be evaluated before it is physically produced thus minimizing time and cost. The results obtained from the FEM modeling will be useful in suggesting design changes in terms of package geometry and choice of packaging materials.
The purpose of this study is to develop an objective method to analyze the thermal cyclic behavior and to evaluate the failure of solder joints in a microelectronic chip. According to the creep results of solder materials, the nonlinear creep constitutive models are established. The three-dimensional thermomechanical analysis of the microelectronic chip under power on-off cycles is conducted, and the time-dependent stress and strain at the solder/substrate interfaces are obtained. Finally, the details that the singular stressstrain promotes the thermal fatigue failures from these interfaces are discussed when compared with the results from fatigue tests.

Package description
The structure of the microelectronic chipset is presented in Fig. 1. It has nineteen pieces of chips, including two pieces of chip Q1, one piece of chip Q2, six pieces of chip Q3, four pieces of chip Q4 and six pieces of chip Q5, respectively. Their working powers are 35.7, 33.    low stress, and power law creep at middle and high stresses. On the basis of the previous literature [17][18], a hyperbolic sine power constitutive model is adopted, in which the relationship of strain rate with stress is linear at low stress and is hyperbolic sine power at middle and high stresses, as shown in Eq. (1). At each temperature T, there exists a critical stress σ v (T), which is used to separate the linear and power law creep stages. According to the creep results of two solder materials Sn3Ag0.5Cu and Pb5Sn, the strain rates under various stress levels and temperature-dependent σ v are determined, as shown in Table 2 [19]. (1) where σ is the equivalent stress, σ v is the linear viscous creep limit, H is the activation energy, R is the universal gas constant, T is the absolute temperature value, and T R is 273 Kelvin (K).

FEM analysis and results
The FEM model of the whole chipset is shown in Fig. 3, and the related material constants are shown in Table 3.
Before the power-driven transient thermal analysis, the coefficients of heat transfer are determined by comparison of the temperatures obtained from numerical analysis and measured results in tests. The chipset maintains power on at the first 30 s, then power off. The measured temperature at the center of the bottom surface increases linearly from 21.      Pb5Sn: Sn3Ag0.5Cu: In the actual power-driven transient thermal analysis, the chipset is repeatedly powered on and off, and both the dwell times are 3 minutes. The transient thermal conduction analysis of the whole chipset is carried out at first, then followed by thermal stress submodel analysis of each chip according to the temperature fields obtained from the thermal conduction analysis of the whole chipset, to get the stress and strain distributions at the solder/substrate interfaces. The boundary conditions in the submodel of each chip are obtained by automatic interpolation of the ANSYS software, as shown in Fig. 4.  5 shows the temperature and strain rate at the center of material 2 (solder Pb5Sn) and 4 (solder Sn3Ag0.5Cu). Due to the shock of power on, high temperature gradient and stress appear in solder Pb5Sn since it is just beneath the power layer. The high stress is presently relaxed because the strain rate reaches a balanced state. After the temperature gets to a saturated state, the strain rate decreases. Because the heat flux is difficult to pass through the thermal insulate layer (material 6) beneath it, the temperature gradient and stress in Sn3Ag0.5Cu solder are very small at the beginning of power on. Therefore, the strain rate at the initial state is very small and gradually increases with the rise of temperature. At the edges around the interface, the heat flux comes from the directions that are not blocked by the thermal insulate layer, as a result, the thermal shock appears. The instant thermal stress and strain distribution in the symmetry plane of chip Q1 at 30 s are shown in Fig. 6, it can be seen obvious stress and strain concentration at the interfacial edge between wafer and Pb5Sn (denoted by E12 in follows), and SnAg3Cu0.5 and Cu (denoted by E45 in follows).    Fig. 7 shows the equivalent stress distribution in materials 1, 2 and 3 near the interfacial edges. The stress concentration is found at the interfacial edge between materials 1 and 2. Fig. 8 depicts the equivalent strain distribution in materials 3, 4 and 5, and we can also see a severe strain concentration appearing at the interfacial edge between materials 4 and 5. Here the failures of solder joints are mainly concerned, it can be understood from the stress and strain distributions that the failures may occur at the interfacial edges of either E12 or E45. Therefore, the singular stress and strain near these interfacial edges need to be investigated carefully. For this purpose, two data points A and B at E12 and E45 are selected, respectively, as shown in Fig. 9.  The severest stress case appears just after power on and finally tends to be steady. Since the normal stress at interface E12 is always compressive, we use the maximum shear stress to define the maximum stress state. Similarly, the maximum traction stress σ t =(σ 2 +τ 2 ) 1/2 is adopted to define the maximum stress state because the normal stress at E45 is tensile. Fig.12 presents the cyclic strain variations of points A and B with power on-off cycles, and the maximum strain state appears just at the moment of power off. The maximum creep strain increase with cycle since the creep strain can accumulate.

.1 Singularity analysis
High stress-strain singularity weakens the connection strength and promotes the crack nucleation from the solder/substrate interface. Therefore, the interfacial singular characteristics, as the key factor affecting the fatigue life, should be discussed in detail. According to the singular field theory, the instant singular stress and strain fields can be expressed as [20] ( ) ( ) where K i (t) and K ε (t) denote stress and strain intensity factors, δ i (t) and ζ(t) are the stress and strain singular orders, r denotes the distance from the interfacial corner, and i=1, 2 denotes the normal and shear stress, respectively. Fig. 13 shows the logarithmic stress distributions along with the distance from the corner at the interfaces E12 and E45. According to the fitting results, the stress intensity factors and singular orders of E12 and E45 are different. Fig. 14 shows the strain distributions at the interfaces E12 and E45, we can see that the singularity of strain is far stronger than that of stress. This fact indicates the strain field may be the dominant factor of failure. The singular orders of stress and strain are different due to the nonlinear constitutive relationships adopted in this analysis.

Figure 14: Logarithm strain distribution
The stress and strain singularities of the five types of chips are analyzed by the above method. The stress intensity factors and singular orders at the maximum stress state are shown in Table 4, where K t is the intensity factor of tensile traction, i.e., σ t =K i /r δ . The strain intensity factors and singular orders at the maximum strain state are listed in Table 5. It is noted that the normal stress at E12 is always compressive, so the stress intensity factor K σ , in this case, has no physical meaning. Since the traction stress combined by the tensile normal stress and shear stress at E45 is the dominant factor for the failure from the interface, it is not necessary to give K τ separately in this case. Regarding the state before power on as the zero stress-strain states, the stress and strain intensity factors listed in Tables 4  and 5 represent the variation ranges dominating the fatigue failure.

Power on-off fatigue failure test
Based on the three-dimensional thermomechanical analysis, the interfaces E12 and E45 both undergo a cyclic creep strain during power on-off cycles. To observe the fatigue failure of the microelectronic chip, the cyclic power on-off tests of the chipset are carried out to observe the failure situation. The dwell times of power onoff at the fatigue tests are set as same as that in the FEM analysis. It is found the fatigue failure of the microelectronic chip causes the increase in electronic resistance, so the in-situ resistance measurement is adopted to determine the fatigue failure when the resistance increase exceeds a specific threshold value that followed by 10

Conclusions
In this paper, we have demonstrated a three-dimensional finite element model that can provide a unique insight into the localized stress and strain concentrations at the solder/substrate interfaces in a microelectronic chip that undergoes power on-off cycles. Based on the calculated stress-strain distributions and singularity parameters, the conclusions are summarized as follows: The variations of interfacial stress-strain fields are time dependent. The maximum stress appears just after the moment of power on and finally tends to be steady. The creep strain continues to increase after power on and reaches the peak value until power off. The singular order of strain is larger than that of stress, owing to the adopted nonlinear stress-strain relationships of the solders. The stress and strain intensity factors and singular orders at E45 are higher than that at E12, indicating that E45 undergoes a more severe stress-strain fluctuation. From the SEM observation of the fatigued chip, the fatigue crack indeed initiates firstly from E45. The test results are in good agreement with that from the FEM analysis, and the fatigue failure of the microelectronic chip is mutually controlled by the singular stress and strain at the SnAg3Cu0.5/Cu interface.