Linearly Tunable CMOS Voltage Differencing Transconductance Amplifier (VDTA)

This paper proposes an alternative way to implement a linearly tunable CMOS voltage differencing transconductance amplifier (VDTA). It has been designed by using the floating current source (FCS) and the current squaring circuit. The circuit achieves its linear tunability by squaring the long-tail biasing current of the FCS. In this way, the transconductance gains of the proposed CMOS VDTA can be varied linearly through adjusting the DC bias currents. As an application example, the proposed VDTA is used in the design of an actively tunable voltage-mode multifunction filter. The derived filter possesses the following desirable properties: simultaneous realization of three standard filter functions; employment of only two grounded capacitors; and electronic tunability of the natural angular frequency and the quality factor. The performance of the proposed circuit and its filter design application were examined by PSPICE simulations with TSMC 0.25-mm CMOS real process technology.


Introduction
A brief review of the recently reported active elements and an introduction to several new controllable elements are given in [1]. Among other things, the voltage differencing transconductance amplifier (VDTA) is one of attractive active devices with two-parameter control [2][3][4][5][6]. This device is a modified version of the previously introduced current differencing transconductance amplifier (CDTA) element, in which the current differencing unit at the input stage is replaced by the voltage differencing unit. Usually, the VDTA solution can be realized by composing two voltage-controlled current sources, which are interconnected internally. Each of them provides two independent transconductance gains (g mF and g mS ), which are electronically adjustable by external DC biasing currents [5]. Therefore, the VDTA element is very useful in active circuit synthesis and quite suitable for electronically controllable analog circuits. Another advantageous feature of this element is that it can easily be used for transconductance-mode solutions due to its input signals being voltages while the output signals are current [2]. Several CMOS reali-zations of the VDTA circuit have been described in the literature [2][3][4]. Previously, the CMOS implementation of the VDTA employing basic floating current sources (FCSs) and supply voltages of ±0.9 V was introduced in [2]. The improved CMOS VDTA was suggested in [3], in which the ideal current sources are realized with swing cascade current mirrors. This kind of current mirrors is used because it has good accuracy and high-output impedance, and the minimum output voltage swing is approximated to 2V DS(sat) [7]. In [4], the design of the CMOS VDTA was also reported, where both transconductance sections were derived from the structure presented in [5]. In this structure, the well-known configuration of multiple-output second-generation current conveyor (MO-CCII) has been supplemented to obtain the required number of current outputs of the first transconductance section. However, their major disadvantage though is the well-known fact that their performance (namely the gain g m ) is directly proportional to the square root function of the external DC biasing current. Due to this the tunability is non-linear, and their linear transconductance ranges are rather limited.
The motivation of this paper is to develop the CMOS VDTA with linearly tunable transconductance. To this aim, the proposed CMOS VDTA utilizes the floating current source (FCS) in its voltage-to-current conversion. In the presented work, the CMOS current squaring functional circuit with the output current proportional to the square of the input current is employed as a biasing circuit for the FCS. The main feature of the proposed VDTA is that it exhibits an ability to linearly tune its transconductane gains by electronic means through the external DC bias currents. To illustrate the application of the proposed VDTA, the design of active voltage-mode multifunction filter with single input and triple outputs is considered. It realizes simultaneously the three standard biquadratic filters namely lowpass (LP), bandpass (BP) and highpass (HP) from each output of the circuit. Orthogonal electronic programmability of w o and Q is also discussed in detail. PSPICE simulations with TSMC 0.25-mm CMOS process parameters are also reported, which demonstrate the linearity and effectiveness of the proposed VDTA and its application.

Basic concept of the VDTA
Basically, the VDTA is an alternative versatile active building block, having five high-impedance terminals, as symbolically shown in Fig.1. The characteristic between terminal voltages and currents can be described by the following matrix relation: where g mF and g mS are the first and second transconductance gains of the VDTA, respectively. In (1), the differential input voltage applied across the p and n ter- is converted to a current flowing out of the z terminal (i z ) by g mF . Similarly, a voltage across the z terminal (v z ) is transformed to the current outward from the x+ and x-terminals by g mS . Assuming that all transistors are properly biased to operate in saturation mode and obey the ideal square-law function, the relation between the output current I SQ and the input current I B is given below. (

Basic functional circuits 3.1 Current-squaring circuit
To guarantee a proper operation, the input current I B is restricted within the range: (3) We observe from eq. (2) that I SQ is the squaring function of I B with the gain equal to (1/8I A ). In addition to eq. (2), the current I SQ is ideally temperature insensitive.

Floating Current Source
Fig .3 shows the circuit diagram of the floating current source (FCS) [11], which will be used as a fundamental circuit for exhibiting the transconductance gain of the proposed VDTA. The circuit can be viewed as two longtailed differential pairs of PMOS and NMOS connected in parallel. It converts the differential input voltage where g mn and g mp are respectively the transconductance values of the NMOS and PMOS transistors, equal to : (5) In above expression, is the average carrier mobility for NMOS and PMOS transistors, C ox is the gate-oxide capacitance per unit area, W and L are the effective channel width and length, and I O is the external DC bias current. Evidently from eqs. (4) and (5), the g m -value of the FCS circuit in Fig.3 is proportional to a square-root of the control current I O .
Substituting eqs.(6) and (7) into (5), and solving for the first and second transconductance gains of the proposed LT-VDTA in Fig.4, the results are : and BS m mS where A p n m Since K m is considered as a constant value, eqs. (8) and (9) imply that the transconductances g mF and g mS of the proposed LT-VDTA can be adjusted electronically and linearly by I BF and I BS , respectively. As was stated earlier, in order for the proposed circuit to operate correctly, the linear operating condition for the input controlling currents I BF and I BS is bounded according to eq.(3).
Owing to the performance of the traditional FCS stage used in the proposed LT-VDTA structure of Fig.4, the output resistances at terminals z, x+ and x-are not high enough for some applications. In order to increase the output resistance level, the improved FCS [12] can be employed for this structure. However, while the output resistance value is improved, the output voltage swing drops by up to V DS(sat) .

Simulations, results and discussions
For all the circuits examined in this work, the computer simulations with PSPICE are performed using model  The CMOS current squaring circuit in Fig.2 is simulated. Fig.5 illustrates the DC current transfer curves of the current squaring circuit in Fig.2, obtained for the input controlling current I B value ranging from -200 mA to 200 mA. It can be deduced from the simulation results that the circuit performs the current squaring operation as expected. In order to demonstrate the linear tuning performance of the proposed LT-VDTA in Fig.4, the simulation for the parameters of TSMC 0.25-mm CMOS technology. The transistor sizes used for simulation are listed in Table 1. Bias voltages were ±V = 1.5 V and bias currents I A were 50 mA.
transconductance g mF is carried out. Fig.6 shows the g mF variations as a function of the input controlling current I BF . In these plots, the simulated results and the expected values are compared, and in good agreement over a considerable input range from 20 mA to 180 mA. It is clear from the curves that the proposed circuit can be tuned linearly by means of the current I BF . The DC transfer functions of the proposed LT-VDTA in Fig.4 are also simulated and shown in Fig.7, with v id (= v p -v n ,) continuously changing from -400 mV to 400 mV, and I BF being equal to 50 mA, 100 mA and 150 mA, respectively. For I BF = 150 mA, the circuit has a linear region over ±180 mV and non-linearity error is less than 9.16%. To study the AC transfer characteristic of the proposed LT-VDTA, the simulated frequency responses for g mS when I BS is swept from 50 mA to 150 mA with 50 mA step size are plotted in Fig.8. According to Fig.8, the useful bandwidth of about 400 MHz can be observed. In addition to the simulation results, the maximum power dissipation is 6.25 mW, when v id , = 180 mV, and I BF = I BS 150 mA. The quiescent power dissipation is 1.34 mW, when v id , I BF and I BS are zero.

Active voltage-mode multifunction filter realization
To demonstrate the effectiveness of the proposed LT-VDTA, an active voltage-mode multifunction filter of Fig.9 is realized as a design example [13]. The circuit consisting of two proposed LT-VDTAs in Fig.4 and two grounded capacitors realizes three standard biquadratic filtering functions, i.e. lowpass (LP), bandpass (BP) and highpass (HP), simultaneously without changing its configuration and without the need to impose component constraints. Straightforward analysis of Fig.9 using eq.(1) yields the following three voltage transfer functions.
and g mFi and g mSi (i = 1, 2) are respectively first and second transconductance gains of the i-th LT-VDTA. It follows from eqs.(11)-(15) that the natural angular frequency (w o ) and the quality factor (Q) of the filter are (17) Figure 9: Actively tunable voltage-mode multifunction filter realization using the proposed LT-VDTAs.
To achieve independent filter parameter control, a proper design can be developed by setting equal transconductances such that g m1 = g mF1 = g mS1 and g m2 = g mF2 = g mS2 , then w o and Q from eqs.(16) and (17) turn to ( The parameter w o can be tuned separately by changing g m2 . The transconductance ratio of g m1 and g m2 can be used for an adjustment of the parameter Q. However, if independent electronic control is needed, only g m1 could be used for Q control. Furthermore, from eqs. (16) and (17), the active and passive sensitivities of w o and Q can be expressed as: Both are low, and equal to 0.5 in magnitude.
As a design example, the multifunction filter of Fig.9 has been realized to obtain the LP, BP and HP responses with the natural angular frequency f o = w o /2p @ 5.50 MHz and the quality factor Q = 1. For this purpose, the circuit components were set to: I B = I BF1 = I BS1 = I BF2 = I BS2 = 70 mA (g m = g mF1 = g mS1 = g mF2 = g mS2 @ 0.66 mA/V), and C 1 = C 2 = 20 pF. The simulated LP, BP and HP amplitude responses of the circuit are shown in Fig.10, where the simulated values of f o were found to have a maximum deviation of 2.83% from the expected values. In this simulation, the total power consumption of the designed filter is about 4.51 mW.

Conclusions
In this work, a linearly and electronically tunable CMOS VDTA circuit is realized. The circuit realization is based on floating current sources (FCSs) for implementing the transconductance stages. The CMOS current squaring circuit is used for supplying the long-tail bias current of the FCs stages. Its transconductance gains are linearly tuned and accurately determined by the external DC supplied currents. The use of the proposed VDTA is illustrated with a realization of an electronically tunable voltage-mode multifunction filter, which employs two VDTAs and two grounded capacitors. PSPICE simulations, performed using TSMC 0.35-mm CMOS technology and confirming the performance of the proposed circuit and its application, are also given.