Back Propagation Neural Network in Predicting the Thermal Fatigue Life of Microelectronic Chips

The present study gives an efficient approach to predict the thermal fatigue lives of microelectronic chips under cyclic thermal load using back propagation (BP) artificial neural network method. Strain based and stress-strain based thermal fatigue life models are established, respectively, according to the experimental results of thermal fatigue tests and the singularity parameters at the failure interface calculated by finite element method (FEM). According to the existing FEM results, the BP approach is configured to predict the singularity parameters at the failure interface in the new chips once the dimensions and thermal-mechanical properties of solders are obtained. By comparison, the predicted thermal fatigue lives according to the established thermal fatigue life models are in good agreement with the experimental results. The thermal fatigue life prediction of microelectronic chips based on the BP network approach is feasible.


Introduction
The electronics industry is mainly driven by the demand for smaller size with lower power consumption while having increased functionality and lower cost. Because of high-density and cost-effective performance, microelectronic chip has been widely used as the core component of automatic control and power converters in various industrial field [1, 2]. Exposed to the switching on-off and random fluctuations of power in the actual operation, the microelectronic chipset is often subjected to cyclic temperature loads. At the same time, the multi-layer package structure inherent in power electronics has an interface layer of a plurality of different materials inside. When the interface layer is under the action of cyclic temperature load, the irreversible plastic deformation accumulates from the interface, due to the mismatch of the coefficients of thermal expansion in different layers. When the cumulative plastic deformation reaches a critical level, the crack begins to nucleate and grow, and finally the device is permanently ineffective [3][4][5][6]. The solder layer plays an important role in the mechanical and electric connections, therefore, its performance, especially, thermo-mechanical properties, has become an important factor affecting the whole reliability of the microelectronic chips. Generally, the strength and failure properties joints are dominated by the properties of both the solder material itself and the interface bonding [7,8]. To obtain the excellent interface bonding, usually the solder material needs to satisfy the following requirements: 1) proper melt temperature; 2) excellent wettability or adhesive properties; 3) enough strength for bonding. Besides, adaptation to surroundings becomes much more important from the social requirements [9,10]. However, such requirements for the solder materials cannot give a quantitative evaluation of strength and thermal fatigue life for older joints. To give a proper estimation of strength and thermal fatigue life, numerical analysis and failure criterion (including thermal fatigue law) are necessary to obtain the parameters describing the stress or strain state and the evaluation criteria [11][12][13]. Since Hattori et al. [14] suggested a singularity parameter approach for the interface reliability of plastic IC packages using two stress intensity parameters that characterize the stress distribution near a bonded edge along the interface, similar methods had been widely adopted to predict the crack initiation or delamination of the microelectronic chip [15,16]. However, such a method, strictly, is based on the concept of point failure, which may difficultly be observed by the physical experiment, and is valid only for the cases that the geometric shape of the solder joints and the loading conditions are the same with that used to build up the fatigue law [17,18]. Meanwhile, the stress intensity factor at the edge of the interface is always dependent on the test condition, assembly geometry, mechanical property of materials and their interactions, as well as the impact of process parameters [19,20], which leads to the result that the precise models and a large amount of calculation are necessary to obtain the stress intensity factors at the failure interfaces of different chips. Soft-computing is doubtless a good alternative for handling this complex problem as it is tolerant of imprecision and uncertainty. Up to date, various soft-computing methods, e.g. artificial neural network [21][22][23], and genetic programming (GP) [24,25] have been used in the field of thermal fatigue.
In the present work, the thermal fatigue life models of microelectronic chips based on interfacial singular stress-strain fields are established. Thermal fatigue tests are carried out to obtain the thermal fatigue lives of the chips, and the three dimensional finite element thermal mechanical analysis is also conducted to get the singularity parameters at the failure interface. Therefore, the parameters in the established model are determined. Also, to save the workload of calculating singularity parameters of new chips, an attempt has been made to predict these parameters by applying the BP neural network approach and accordingly, the thermal fatigue lives of these chips can be calculated.

Thermal fatigue prediction model 2.1 Thermal fatigue test
Five types of chips, denoting as I-V chips, are packaged in one chipset. The working powers of I-V chips are 35.7, 33.3, 25.8, 20.0 and 14.5 w, respectively. Each chip has the same layered stacking structure, and the materials from top to bottom are, in order, silica gel, wafer (silicon), solder Pb-5Sn, Cu, solder SnAg3Cu0.5, Cu, insulate layer, and the substrate, as shown in Fig. 1. Before the thermal fatigue tests, the silica gel protector is cleaned and the chips are cut out from the chipset by a wire cutter. The cyclic temperature varies from -40 to 90 o C in the thermal fatigue test, as shown in Fig. 2. It is accomplished by the specially designed heating box inserted in a bigger low temperature container which is always kept -40 o C by the liquid nitrogen. When the chips are heated, the sliding door of the heating box is close, the embedded heating tubes work. When cooled, and the sliding door is open and the heating tubes are powered off. All the chips are put into a same heating box to undergo the cyclic temperature load.  To detect the fatigue failure, the electric resistance of the chips measured by a digital resistance meter for certain intervals. According to the sketch of electronic resistance variation during the thermal cycles, the crack morphology of chip IV when the electronic resistance increasing (RI) reaches 10 % and 15 % are respectively observed by the JSM-6301F scanning electron microscope (SEM) (JEOL, Tokyo, Japan). The samples are covered by carbon before and the analysis is conducted under 20 kV in the SEI mode, the observed SEM images are shown in Fig. 3. It can be seen that many micro-cracks appear at the interface between the wafer and solder Sn-5Pb (E12) at 10 % RI, and the micro cracks have gradually merged into a main crack when RI reaches 15 %. While at this time micro cracks start to appear at the interface between solder SnAg3Cu0.5 and Cu (E45). The locations of the E12 and E45 have been demonstrated in Fig. 1, and the representative data points at the E12 and E45 are also selected to analyze the connection between cyclic stressstrain variations from FEM analysis to the experimental thermal fatigue cracking. It is interesting that the main crack also comes into being firstly from the E12 in the other four chips. For the convenience, we define the fatigue life limit Nf when the electronic resistance increasing reaches 15 % [26]. Fig. 4 shows the measured electronic resistance variations of each chip, and the tested fatigue life Nf is listed in Table 1.

FEM analysis
Three dimensional thermal conduction and thermal stress analysis have been carried out to obtain inter-facial stress-strain fields of the chips undergoing the cyclic thermal load. The load condition is the same as what applied in the thermal fatigue tests. Here IV chip is taken as an example to depict the general features.
To obtain the accurate stress and strain distribution at the interface, FEM submodel analysis is carried out, and the boundary condition of the submodel is obtained from the former thermal conduction and stress analysis of the whole chipset by automatic interpolation, as shown in Fig. 5.  6 shows the stress variation at the E12 and E45 with thermal cycles, where σt=(σ 2 +τ 2 ) 1/2 donates the maximum traction when the normal stress is tensile at the interface. It can be found that the E12 is under compress, while the E45 is under tension at the heating According to the instant singular field theory [27][28][29], where K i (t) and K s (t) denote the stress and strain intensity factors, δi(t) and ς(t) are the stress and strain singular orders, i = σ, τ denotes the normal and shear stress, respectively, and r denotes the distance from the singular edge.
Picking up the stress and strain distributions at the corresponding steady states along the interface edge, the step. However, the opposite is true at the cooling step. There are two stress shocks, one is in the heating process and the other in the cooling process. The second shock is much stronger than the first one. The stress near the edge varies in the first several cycles, but it is saturated after 3 cycles. Fig. 7 shows the variations of Mises stress and equivalent strain at the E12 and E45. It can be seen that the stress range is severe at the E45, but the strain range is severe at the E12 since Pb5Sn is softer. Therefore, it follows that the actual fatigue failure mode is determined by the coupling stress and strain controlled mechanism.

Thermal fatigue models based on interfacial singularity
Thermal cycles lead to the coupled stress and strain cycles, though their peaks do not appear simultaneously, which attributes to the visco-properties of solder materials. This fact means that both stress and strain cycles contribute to thermal fatigue failures. Instead of using stress or strain as the parameters for thermal fatigue life evaluation, here the stress and strain intensity factor ranges and their corresponding singular orders are adopted to formulate the thermal fatigue law. At the interface edge, the ranges of stress and strain are written as For the materials with tiny defects, the fatigue strengths and thresholds of fatigue crack propagation match those without defects. Namely, only several points with large stress in materials generally cannot affect fatigue characteristics. Therefore, using the stress-strain range within a region to describe the thermal fatigue behavior is more accurate than only by one or two points.
Here the concept of characteristic length of fatigue failure is introduced, i.e., when the average stress or strain range within a characteristic length l arrives at or exceeds the fatigue limit, the thermal fatigue crack begins to initiate or propagate [30]. The average stress range σ ∆ within l at the interface edge can be expressed as If a unit length is taken, Eq. (3) can be simplified as max min max m in 1 1 Then the range of stress and strain intensity factors can be written as where DK s and DK t represent the multi-axes effects when both normal and shear stress are considered.  Therefore, strain-controlled and stress-strain controlled fatigue laws are respectively considered, as shown in Eqs. (6)(7).
where m 1 , m 2 , C ε , and C εσ are constants determined by test results.
By fitting the results of thermal fatigue tests and the singularity parameters at the failure interface obtained from FEM analysis, one obtains Theoretically, once the stress-strain intensity factors and their singular orders at the failure interfaces of new chips are obtained, their thermal fatigue lives can be predicted. However, the calculation of thermal mechanical analysis to get the singularity parameters at the failure interface is not easy and time-consuming for the engineers. Therefore, a BP neural network based method is necessary to be established for the singularity parameters to predict the thermal fatigue life.

BP model for thermal fatigue life prediction 3.1 Principle of BP neural network
The classic BP artificial neural network is a three or more than three layers hierarchical forward neural networks (i.e. including an input layer, an output layer, and one or more hidden layers). The algorithm consists of two parts: the forward transmission of information and the back propagation of errors. In the forward transfer process, the input information passes to the output layer through the hidden layer. If the desired output is not obtained at the output layer, the error change value of the output layer is calculated, and the network passes the error signal back along the original connection path and modifies the weight of neurons in each layer until the desired goal is reached [31]. Therefore, it is user-kind to clear these mathematical difficulties by a black box. Since the singular orders and intensity factors can be expressed in following form, ( ) , = load condition, geometry, material properties, It is possible to estimate the singular orders and intensity factors by a trained neural network instead of FEM analysis. However, to train an efficient neural network, a huge amounts of FEM analysis results as the samples for training are necessary. That is, the user can obtain the singular orders and intensity factors of new chips simply through the well trained neural networks.

Variables in BP model
The logical route of the developed method is shown in Fig. 8. To reach the stated goal of BP network predicting the stress-strain intensity factors and their singular orders, four variables, i.e., elasticity of modulus E, thickness t and width w of solder Pb-5Sn, and cyclic temperature range ΔT, are considered and used as the parameters of the input layer of BP network. According to the different values of input variables, 60 sets of samples are prefabricated from FEM simulation, among which 50 sets are selected as training data, and the remaining 10 sets are used as test data.

Predicted results
The BP model for thermal fatigue life prediction is accomplished by the MATLAB neural network toolbox. The parameters of BP network, including the neuron number in the hidden layer, target error, learning rate are set to 13, 0.0001, and 0.35, respectively. When the testing results meet the accuracy requirement, the trained BP network can be used to predict the singular orders and intensity factors in different stages. The detailed input data of the chips to be predicted are listed in Table 5, and the predicted intensity factors (Kσ, Kτ, Kε) and their corresponding singular orders (δσ, δτ, ε) of E12 at steady states are depicted in Figs. 9-11, respectively. The FEM results of these chips are also listed for comparison. The average predicting error of Kσ, Kτ, Kε and δσ, δτ, ε at the heating and cooling stages are 2.13 %, 3.32 %, 5.04 %, 2.04 %, 4.89 %, 3.67 %, 4.78 %, 1.67 %, 1.31 %, 2.87 %, 1.93 %, and 3.90 %, respectively, indicating that the trained BP neural network can predict the stress-strain intensity factors and singular orders at the failure interface with good accuracy.
When the singular parameters at the heating and cooling stage are predicted, the thermal fatigue lives of the chips can be calculated by Eqs. 8-9, as listed in Table  6. When compared with the tested results, the stressstrain controlled fatigue law can get more accurate predicting results than strain controlled one straincontrolled, indicating that the thermal fatigue failure of the chips is not just governed by strain, but by the mutual effect of interfacial stress and strain. On the whole, the differences between the predicted outputs and experimental results are quite small. The thermal fatigue life prediction method of microelectronic chips based on the BP neural network is feasible.

Conclusions
The present study gives an efficient approach for the thermal fatigue lives prediction of microelectronic chips under thermal cycles using the BP method. Ther-mal fatigue tests and FEM stress-strain singularity analysis at the failure interfaces are conducted to establish the interfacial singularity based thermal fatigue life prediction model. To save the calculation, a BP neural network model is established to predict the interfacial singularity parameters of new chips. The results show that the established BP method can effectively predict the necessary singularity parameters for thermal fatigue life evaluation. Strain-controlled and stressstrain controlled thermal fatigue models can both give reasonable prediction. The application of the thermal fatigue models demonstrates a fact that the thermal fatigue of chips can be evaluated uniformly no matter what the shapes, dimensions and the thermo-mechanical properties of the solders are, as long as the relevant stress-strain intensity factor and singular parameters at the failure interface can be obtained.
However, as the outcome of numerical analysis and experimental results, the thermal fatigue model involves several factors such as the local interfacial singularity, the diversification of singular field parameters in the FEM analysis, and the measurement of thermal fatigue life during physical experiments throughout the modeling process. Further research based on other computational intelligence approaches, like computational intelligence aided design, can be employed to predict thermal fatigue lives under different loading conditions.

Acknowledgements
This research work was supported by the National Natural Science Foundation of China (No.51404286), and the Fundamental Research Funds for the Central Universities of China (No.17CX02065).

Conflict of interest statement
The authors declare no conflicts of interest.