Electronically Adjustable Capacitance Multiplier Circuit with a Single Voltage Differencing Gain Amplifier (VDGA)

Abstract: In this work, we propose a resistorless realization of a simple electronically adjustable capacitance multiplier circuit using a single voltage differencing gain amplifier (VDGA) as an active building block. The circuit utilizes one VDGA and only one capacitor in a simple circuit configuration. The proposed capacitance multiplier circuit can be tuned electronically with the adjustment of the transconductance gains of the VDGA. To emphasis the applicability of the proposed circuit, a second-order RC low-pass filter is constructed as an application example. PSPICE simulations are performed to verify the theory.


Description of the VDGA
The VDGA, whose circuit symbol is represented in Fig.1, is a recently reported active building block introduced in [22]. In ideal operation, the behavior of the VDGA element can be characterized by the matrix equation: where g mA and g mB denote the transconductance gains and β represents the voltage gain of the VDGA. Internal structure of the VDGA based on MOS transistors is depicted in Fig.2 where Bk ik KI g = , for i = 1,2, 3, 4. (3) In equation (3), K is the transconductance parameter of the transsitor and I Bk is an external DC bias current. It is worth mentioning that the transconductance g mk is tuned electronically by changing the bias current I Bk .
The FCS M 1A -M 4A allows for having the differential-input voltage to current converter by i z = g mA (v p -v n ), while the FCS M 1B -M 4B performs the transconductance amplifier action between the z and x terminals (i.e. i x = g mB v z ). Furthermore, a pair of FCSs M 1B -M 4B and M 1C -M 4C allows us to obtain a current-controlled voltage amplifier behavior (v w = βv z ) with the voltage transfer gain equal to β = g mB /g mC . Of course, the gain β can be adjusted simple by setting the g mB to g mC ratio.

Proposed capacitance multiplier circuit
The proposed topology of the capacitance multiplier with a single VDGA is shown in Fig.3. It consists of only one VDGA and one floating capacitor. Although the floating capacitor is required, it can be implemented using metal-oxide-metal (MOM) double poly (poly1-poly2) or metal-insulator-metal (MIM) capacitor process [24]. Considering the VDGA port relation (1), the input impedance of the proposed capacitance multiplier circuit is where the simulated equivalent capacitance C eq is equal to: It is clear that the proposed circuit in Fig.3 implements a variable capacitance multiplier with a capacitance multiplication factor given by: With this expression, the capacitance multiplication factor K is scaled electronically by setting the transconductance ratio g mA /g mC .

Analysis of non-ideal behavior
Deviations from the ideal circuit performance are mainly due to the voltage and current transfer inaccuracies and the parasitics of the VDGA. The non-ideal transfer gains of an actual VDGA are expressed as: where α A and α B are the non-ideal transconductance gains and δ is the non-ideal voltage transfer gain. If these non-ideal transfer gains are considered, then the non-ideal input impedance can be rewritten as: In this case, the equivalent capacitance value changes to: Another non-ideality is introduced by the parasitic impedances at VDGA terminals (Fig.4). Parasitic resistances R p , R n , R z , R x and the parasitic capacitances C p , C n , C z , C x are connected between the high-impedance terminals (p, n, z and x) and ground. Series parasitic resistance R w is associated with the w-terminal. If these parasitic impedances are taken into consideration, the non-ideal performance of the proposed circuit in Fig.3 can then be evaluated as follows.
If only the p-terminal parasitic impedances are considered, the equivalent capacitance is obtained as: Similarly, if only the z-and x-terminal parasitic impedances are taken into account, the equivalent capacitance can be computed as: where If only the effect of R w is considered, the equivalent capacitance is : By considering equation (10)- (12), it can be seen that the various parasitics exhibited at different terminals of the VDGA will affect the high-frequency behavior of the proposed circuit. However, from equation (10), the influence of the p-terminal parasitic impedances on the simulated capacitance can be reduced sufficiently under the assumption that R p >> 1, and by choosing the external capacitor such that C >> C p . We also observe from equation (11) and (12) that the presence of parasitic impedances at terminals z, x and w introduces two extra poles, which reduces the useful bandwidth of the proposed circuit. Therefore, the circuit behaves as a capacitor for frequencies:

Simulation results and application
The behavior of the proposed circuit in Fig.3 has been simulated with PSPICE using the transistor model parameters of a 0.25-µm TSMC CMOS process. Transistor dimensions are given in Table 1 and symmetrical supply voltages are +V = -V = 1 V. The proposed capacitance multiplier circuit depicted by Fig.3 was simulated with the following component values: I BA = I BB = 100 µA (g mA = g mB = 1 mA/V), I BC = 4 µA (g mC = 0.2 mA/V) and C = 50 pF, which results in C eq = 0.3 nF. The quiescent power consumption of the circuit was 1.09 mW. In Fig.5, the simulated transient waveforms for v in and i in with a frequency of 10 MHz are given, wherein the phase difference has been found to be 89°. Fig.6 also represents the simulated frequency responses for Z in , compared with that of an ideal capacitor response. It is observed from Fig.6 that the simulation results are in very close agreement with the theoretically predicted response far beyond 10 MHz. In addition to illustrate a variation of the C eq value versus  Fig.3. Figure 6: Simulated frequency responses for Z in of Fig.3.
the capacitance multiplication factor, the impedance magnitude responses with different values of g mA are depicted in Fig.7. The results are plotted for the circuit parameters listed in Table 2.  An illustrative application of the proposed capacitance multiplier circuit in Fig.3 is the realization of a second-order RC low-pass filter depicted by Fig.8. The cut-off frequency point is determined by: f c = 1/2π(R 1 R 2 C eq1 C eq2 ) 1/2 . In this realization, the capacitors C eq1 and C eq2 are realized with the proposed capacitance multiplier circuit in Fig.3. The simulations of the illustrative low-pass filter have been performed by keeping R 1 = R 2 = 1 kΩ, and varying the values of C eq = C eq1 = C eq2 . Fig.9 shows the simulated voltage-gain responses for C eq = 0.13 nF, 0.30 nF and 0.67 nF, where detailed C eq settings are the same as those given in Table 2. The results indicate that the value of f c is: 1.37 MHz, 0.53 MHz and 0.23 MHz, respectively for different sets of C eq values.

Conclusions
In this work, a simple realization of an adjustable grounded capacitance multiplier is introduced. The configuration uses only one VDGA as an active element and one floating capacitor as a passive element. The capacitance multiplication factor is electronically tunable by the ratio of the VDGA's transconductance gains. The effects of the VDGA non-idealities including voltage and current transfer errors and parasitic elements on

Conflict of interest
The authors confirm that this article content has no conflict of interest.