DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier

Analog multiplication circuits are very important blocks widely used in analog signal processing applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to the supply voltage. In this work, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors. The proposed circuit is laid out with 491.4 μm2 chip area. Post layout simulations show that the proposed circuit has high bandwidth (1.2 GHz), low supply voltage (0.2 V), and low power consumption (44.6 μW). In addition, the proposed circuit is examined for temperature variation, total harmonic distortion, intermodulation products and Monte Carlo analysis of the dimensioning of the circuit. The post layout results show that the proposed circuit has promising performance against its counterparts in the literature.

where x and y are two continuous input signals and K is a constant value appropriately dimensioned. Analog multipliers are classified according to the polarization of their inputs. The classifications are as follows: i) One quadrant [1] whose inputs are non-polarized, ii) Two quadrant [2], [3] whose one of the inputs are polarized, iii) Polarized both inputs are called four quadrant [4][5][6][7]. In addition, the multipliers are divided into two types: current mode [8], [9] and voltage mode [4][5][6][7].
The first bipolar analog multiplier known as the Gilbert cell was published in 1968 by Barrie Gilbert [10]. Since analog multipliers based on CMOS technology have been classified (i) according to the form of the input signal; current or voltage mode (ii) with regard to the operating region of the transistors; weak inversion [8], [11], [12] strong inversion [13], [14], saturation region [15] and linear region [16], [17]. Although the input signal range and bandwidth of analog multipliers operating in the weak inversion region are quite narrow, they are frequently used in low power consumption applications. Analog multipliers operating in the saturation region have wide bandwidth, dynamic input range and high speed. In multipliers operating in the strong inversion region, the error caused by the body effect causes mismatch in the threshold voltage.
In recent years, the increasing popularity of portable devices such as smartphones and tablet computers has brought restrictions on battery capacity, weight and size. It has created serious restrictions on power consumption and led to the emergence of low-power and high-performance circuitry techniques. Thus, several methods have been suggested to concentrate the power consumption of the analog multipliers. Some of these techniques are as follows: weak-inversion [8], [11], [12], [18], subthreshold MOSFETs [19][20][21][22][23], bulk driven [11], [12], DTMOS [24] [25], and floating gate MOSs [5], [26], [27]. It is seen that transistor multipliers working in weak inversion region have poor dynamic range, limited voltage swing and low bandwidth. In the study of Soltany and Razai [12], although the power consumption was reduced by bulk-input, it was seen that the speed and output voltage range were also very low. Even though, analog multipliers designed with transistors operating in the subthreshold region [19][20][21][22][23] show low power consumption, but the dynamic range and operating speed of the multiplier are low. In the study, using DTMOS transistor [24], low power consumption and full-scale input voltage were provided, but -3dB bandwidth was obtained as 1.11 MHz. In articles [26] and [27] a low power consumption analog multiplication circuit was implemented using FGMOS, but their bandwidth was specified as 10 MHz and 200 MHz, respectively. In the study of Keles and Kuntman [5], FGMOS technique has been achieved with high bandwidth such as 1.5 GHz, but there is no information about power consumption here.
In this article, a low power, wide bandwidth four-quadrant analog multiplier by using DTMOS based folded Gilbert cell is proposed. The simulation results are given using Cadence Environment using 0.18 μm TSMC CMOS technology under a supply voltage of 0.2 V.
Gilbert cell is one of the first studies of analog multiplication circuits proposed by Barrie Gilbert in 1968 [10]. Gilbert cell is popular in bipolar integrated circuits (IC) due to its wide dynamic range and bandwidth. In this study, the analog multiplier was realized with the folded Gilbert cell by using DTMOS technology and the bandwidth is obtained pretty much wider.
Due to undesirable behavior in nonlinearity, the range of the input signal is limited to half or generally much less of the supply voltage. In this study, full-scale supply voltage can be used for an input signal range [26]. In order to demonstrate its technological strength, Monte Carlo analyses were performed in AC form with 10% mismatch of process parameters (t ox and V TH ) and transistor widths.
The rest of the paper is arranged as follows: Information on the DTMOS structure and the proposed multiplication circuit structure as well as equations are given in Section 2. AC/DC characteristics, intermodulation products, temperature sensitivity, total harmonic distortion and Monte Carlo analysis are given in Section 3. Finally, Section 4 concludes the paper.

DTMOS based four-quadrant analog multiplier
Today, the increase in the use of portable devices has brought limits on battery capacity, weight and size. These restrictions have contributed to an increase in studies on low power and high performance circuit techniques.
The need to reduce power consumption has led to a reduction in the supply voltage of the circuits. Excessive lowering of the supply voltage causes standby power and speed problems of the memory elements. MOS-FET with dynamic threshold voltage was proposed by Assaderaghi et al. in 1994 to meet low voltage performance requirements [28]. The topology and symbol of the DTMOS obtained by connecting the body and gate of a MOSFET are given in Figure 1.
The threshold voltage of DTMOS is as follows: V th is threshold voltage, V t0 is the zero body bias threshold voltage. γ is the body effect coefficient and it depends on the gate oxide capacitance, silicon permittivity and substrate doping ф F . is the Fermi potential. V SB is the source to body voltage. The threshold voltage equation is written for a long channel NMOS transistor where drain-induced barrier lowering (DIBL) effect is neglected. The proposed DTMOS has a high threshold voltage at zero bias and low threshold voltage when the gate-source voltage is equal to supply voltage( V gs = V dd ) [29].
By reduction of threshold voltage, inversion charge (Q N ) is increased; so, larger inversion charge leads to a higher current drive in DTMOS in comparison to the regular MOSFETs MOS transistor's drain current is given by below Eq. (2).
According to the equation the transistor will saturate in weak inversion when V DS ≥ 3kT/q [17]. Under some limitations, bulk-DTMOS technique can be applied to cheap standard CMOS fabrication process without additional processing steps. The transconductance g m is described by DTMOS reduces the junction width and consequently the depletion region charge density, which contributes to a decrease in the threshold voltage. In case of reverse bias, the depletion region width increases, and the increase in the body charges causes the threshold voltage to increase. DTMOS-based circuits in case of forward biasing, the threshold voltage will be low. When the transistor is turned off, the V TH becomes high, resulting the leakage current will also be low. Thus, the threshold voltage is changed dynamically with respect to the gate input, whereas operating state of the circuit is also changed.
The DTMOS based four-quadrant analog multiplier circuit by using the folded Gilbert cell is presented in Figure 2. M3-M4 forms one differential pair, while M5-M6 transistors form another differential pair. The drain of M3-M5 and M4-M6 transistors are cross connected. The input signal V X is applied to the cross connected differential pairs, while the input signal V Y is applied to another differential pair consisting of M1 and M2. The bias currents (I SS1 , I SS2 , I SS3 ) are the tail currents and I SS1 = I SS2 = I SS3 . The output current expression of the circuit is: Where k n and k p are the transconductance of the nchannel and p-channel transistors, respectively. k n = (µ n C OX /2)(W/L), µ n , is the electron mobility, C OX is the gate oxide capacitance of the NMOS transistor. W and L are the width and length of the NMOS transistors, respectively.  Table 1. Layout of the proposed DTMOS based Analog Multiplier is given in Figure 3.  The DC transfer characteristic of DTMOS based analog multiplier is given in Figures 4 and 5. For the proposed multiplier topology, the transfer curve I OUT versus V X and I OUT versus V Y are shown in Figure 4 and Figure 5 respectively. In Figure 4,  In order to evaluate the AC transfer characteristics of DTMOS based analog multiplier, the input voltage V X 100 mV DC is kept constant while the other input voltage V Y 100 mVp-p AC is applied. The frequency response characteristics of the analog multiplier are shown in Figure 6. -3 dB bandwidth of the proposed structure is 1.4 GHz and 1.2 GHz for the schematic and post layout simulations respectively.
To evaluate the performance of the DTMOS-based analog multiplier as an amplitude modulator, two sinu-soidal signals with 200 mV amplitude at 10 kHz and 300 kHz frequencies were applied to the inputs, respectively. The multiplier can be used as a modulator is shown in Figures 7 and 8.
Intermodulation distortion for analog multipliers is a performance criterion just like total harmonic distortion. Ideally, the total harmonic distortion at the output of a multiplier is zero and no intermodulation products are presented. Intermodulation products arise as a result of the non-linearity of analog multipliers. Table 2 Figure 4: DC characteristics of the proposed multiplier versus V X with V Y as a parameter. DC voltage of 200 mV was applied to the V Y input, while a sinusoidal signal with a frequency of 1 kHz, 10 MHz and 100 MHz were applied to the V X input. The THD of the output voltage of the proposed multiplier is given in Figure 10 as a function of the input signal. THD [%] is composed of 9 harmonics and it is considered that the maximum THD is below 3% for the total scope of the input signal.
In order to evaluate the performance of the proposed multiplier as a frequency doubler, a sinusoidal signal of 100 mV amplitude and 10 kHz frequency was applied to both inputs of the multiplier. The accuracy of the frequency doubler function for the proposed multiplier is indicated in Figure 11.
The variation of AC and DC characteristics of the proposed multiplier with temperature is investigated. The temperature changes from 0 to 100 ° C, while the change in AC characteristic is shown in Figure 12. The DC characteristic change in the same temperature   shows the 2 nd , 3 rd , 4 th and 5 th degree intermodulation products of the signal at the output of the proposed multiplier. Two sinusoidal signals were applied to the inputs of the analog multiplier at frequencies f 1 = 10 kHz and f 2 = 300 kHz. Furthermore, the frequency spectrum of the output of the proposed multiplier is given in Figure 9.
To evaluate the total harmonic distortion (THD) of the output signal of the proposed multipliers, a constant  The statistical distribution of the width (W) of the proposed multiplier circuit for 10% mismatch is given in Figure 13 for 200 runs. The histogram showing the statistical distribution in Figure 14 according to the 10% mismatch change in transistor width is given in Monte  Carlo analyses. According to the histogram, maximum bandwidth reaches up to 1.309 GHz whereas minimum bandwidth is 1.105 GHz. Also, average value is given as 1.230 GHz according to the post layout simulations. In addition to the 10% mismatch in width (W), the analysis made by adding 10% mismatch change in t ox and V TH process parameters is presented in Figure 15. In the histogram showing the statistical distribution here, the maximum bandwidth is 1.360 GHz and the minimum bandwidth is 1.114 GHz respectively. The average bandwidth is 1.23 GHz. All simulations have been done with post layout simulations.
where bandwidth is in (MHz), THD in (%), supply voltage in (V), and power consumption is evaluated in (µW). The FoM value of the proposed multiplier out-performs the other multipliers in the literature. Table  3 shows the comparison of the multiplier according to FoM value and various performance criteria with the existing multipliers in the literature. The circuits with higher FOM values are superior to the others. According to this, the FoM value of the circuit we recommend is 162.08, while the FoM value of the nearest circuit [30] is nearly four times less.

Conclusion
In this study, a four-quadrant analog multiplier in with voltage input and current output is presented. The circuit is designed using dynamic threshold MOS and folded Gilbert cell structure. The circuit has advantageous parameters such as wide bandwidth, low supply voltage, low power consumption and low THD. Also, the proposed structure is tested in various applications to evaluate circuit performance. Intermodulation products are given to show the efficiency as a modulator.
Compared with the studies in the literature, it stands out with its wide bandwidth and low power consumption.

Acknowledgement
All simulations have done with Cadence Design Environment in 0.18µm TSMC CMOS technology. In this respect, we are thankful to Istanbul Technical University VLSI Laboratories for the Cadence Design Environment support.

Figure 14:
The bandwidth distribution of analog multiplier depending on MOSFET widths (W) Figure 15: The bandwidth distribution of analog multiplier depending on process parameters (t ox and V TH ) and MOSFET widths (W)