Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/ off current ratio (ION/IOFF) and steeper subthreshold swing (SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.


Introduction
With the continuous development of integrated circuits (ICs), device sizes have been gradually shrinking. The performance of traditional metal-oxide-semicon-ductor field-effect transistors is approaching its limit. The off-state leakage current is increasing exponentially caused by the short-channel effect (SCE), resulting in unacceptable static power [1]. At the same time, it has become difficult for inversion-mode field effect transistors (FETs) (IMFETs) to achieve ultra-deep doping concentration gradients at the device junctions, inducing increasing thermal budget [2]. To overcome these obstacles, some novel device structures have been proposed, including junctionless FETs (JLFETs) and ferroelectric negative-capacitance FETs (NCFETs) [3]- [5].
Compared with traditional inversion-mode transistors, JLFETs have stronger immunity to the SCE [6]. In the actual manufacturing process, there is no super-steep junction, and no additional dopants must be injected into the source and drain regions because the source and drain have the same doping polarity and concentration as the channel. Thus, JLFETs have a simpler manufacturing process and a lower thermal budget than IM-FETs [7]. In JLFETs, the majority carriers are conducted in the center of the channel instead of the surface, and the majority carriers in the channel are completely depleted by the gate bias to shut down the device. Moreover, the multigate structure can effectively improve the gate-tochannel control capability, so JLFET devices usually use a double gate to achieve complete channel depletion [8]. It has been verified that the gate metal of JLFETs must have a work function greater than 5.0 eV to completely deplete the Si body to reach the off state [2]. However, it is difficult for a gate metal with a relatively large work function to meet the thermal stability requirement and achieve good adhesion to the gate dielectric [7]- [9]. Therefore, a novel mechanism or structure must be found to overcome this problem.
Since the NCFET was first proposed [4], there have been many reports on both IM and JL structures. A new transistor concept is proposed that combines ultra-thin body and NCFET in [10], It has been proved that performance improvement with low-power NCFETs is realized by amplifying the internal gate voltage caused by the negative-capacitance effect. Hu et al. studied the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs) in [11]. In our previous studies, we discussed the capacitance matching problem caused by the change of ferroelectric parameters in IM devices, and the performance of NCFET in RF applications [12,13]. Yejoo Choi studied the electrical characteristics of NC-JL-NWFET based on HfO2 through TCAD and MATLAB simulations [14].
In addition, some studies have shown that additional source-drain doping (N S/D ) of a JLFET can increase the on-state current, but it also causes the higher subthreshold swing (SS) and the drain induced barrier lowering (DIBL) effect to become more prominent [15,16]. NCFETs can achieve steep SS and improve the DIBL effect, while greatly reducing operating voltage and power con-sumption [17]- [18]. Therefore, by combining the above two points, the advantages of NCFET can offset the negative effects brought by the additional source-drain doping of JLFET, which can make NC-JLFET have more excellent performance. However, the effect of structure adjustment, such as additional source-drain doping, on the performance of an NC-JLFET has not yet been understood. So, in this work, we construct an NC-JLFET by stacking ferroelectric layers on the gate of the baseline JLFET and investigate the influence of additional sourcedrain doping on its electrical characteristics. Using Sentaurus TCAD simulation, it is demonstrated that additional source-drain doped NC-JLFETs have improved performance over traditional JLFETs, such as higher I ON / I OFF , steeper SS, and negative DIBL. Figure 1a shows a two-dimensional diagram of an NC-JLFET using a metal-ferroelectric-metal-oxidesemiconductor (MFMIS) structure. The material of the insulating layer is SiO 2 ; the channel, source, and drain are all N-type doped; source, drain, and channel. The channel is uniformly doped and the concentration remains fixed at 1 × 10 19 cm −3 . The source and drain are additionally doped with a concentration range of 1 × 10 19 -5 × 10 19 cm −3 .  Table I lists other specific device parameters for the proposed NC-JLFET. Among them, the parameters of the baseline transistor JLFET are the gate length Lg=28nm, the silicon channel thickness W=10nm [14], and the metal work function WK is 5.0eV [2], these values of Pr and Ec are in the same range as those of ferroelectrics such as Hf-and Zr-based binary oxide ferroelectrics [11]. It is assumed that the inner and outer metals have the same work function and that the work function variation is not considered. Figure 1b is a schematic of the equivalent capacitance of the NC-JLFET, where C FE is the ferroelectric layer capacitance and C MOS is the gate equivalent capacitance of the baseline JLFET, including the insulation layer capacitance (C ox ) and channel depletion capacitance (C dm ). V gs and V int are the external gate voltage and internal node voltage, respectively. The baseline JLFET is connected in series with the ferroelectric capacitor to form the NC-JLFET. The Landau-Khalatnikov (LK) equation with Gibbs free energy is the standard model of the ferroelectric capacitor, specifically described as the electric field in a ferroelectric as a function of polarization [19]:

Device Structure and Simulation
where α, β, and γ are material-dependent parameters of the ferroelectric, α=-3√3/4 x E c /P r , β=-3√3/8 x E c /P r 3 , and γ = 0 [20], the values of which fit the parameter range in HfO 2 -based ferroelectrics [21]. The voltage across the ferroelectric capacitor can be obtained from:  pendence, high-field saturation (velocity saturation) and considering the silicon bandgap narrowing, the old Slotboom model of band gap narrowing and the Shockley-Read-Hall model for recombination generation are also considered. In view of the highly doped source-drain regions, Fermi (also called Fermi-Dirac) statistics is necessary to make it more physically accurate. In addition, because the device dimension is very small, some quantum modification terms (eQuantum-Potential) are added for the simulation results to be closer to the real condition.  cation contributed by the ferroelectric layer. As shown in Fig. 2d, the on/off current ratio (I ON /I OFF ) of JLFETs increases with increasing N S/D because increased N S/D reduces the resistance of the source and drain, which increases the drive current. This trend is also in line with the conclusions obtained in [16,22]. However, for NC-JLFETs, the I ON /I OFF decreases as N S/D increases. This is because increased N S/D values induce doping-dependent electron mobility degradation [14]. Moreover, as the source and drain doping concentrations increase but the channel concentration remains constant, the I ON / I OFF values do not change much. When N S/D = 5 × 10 19 cm −3 , the I ON /I OFF value of the NC-JLFET is still larger than in the JLFET by a factor of nearly 10 3 .

Results and Discussion
where C ox is the gate oxide capacitance and C dm is the depletion capacitance. As is well known, in JLFETs, the higher the doping concentration, the larger the C dm , and therefore the larger the SS. In contrast, in NC-JLFETs, the larger the C dm , the greater the increase of C dm /|C FE | compared with the increase of C dm /C ox , so the smaller the SS will be, that is, less than 60 mV/dec. This is the same as the change trend of SS caused by different doping concentrations of NC-JLGAAFET in [14].
For conventional JLFETs, when the drain voltage (V ds ) increases, the source-drain depletion layer width is close to the channel length, which reduces the source barrier height. The decrease of the barrier height allows the source electrons to easily cross the barrier to reach the drain, and the channel charge controlled by the gate voltage is reduced, which leads to increased leakage current and lowered threshold voltage. This mechanism is known as the DIBL effect. For traditional JLFETs, increasing V ds will tend to increase current (I ds ), as can be seen in Fig. 4a. However, for NC-JLFETs, the relationship between the V gs and V int is: where V FE is the voltage across the ferroelectric. Owing to drain and channel coupling, when V ds increases, the gate charge decreases, which results in a decrease in V FE . In addition, the V int will also decrease, as shown in  can be clearly seen that negative DIBL characteristics appear when T FE = 2nm and 3 nm.
At the same time, negative DIBL can also be proved by comparing the potential distribution in the channel region of JLFETs and NC-JLFETs as shown in Fig. 6. For a traditional JLFET, the potential barrier height will decrease with increasing V ds . For an NC-JLFET, the opposite trend is shown in Fig. 6b. That is, with increasing V ds , the height of the barrier near the source will increase causing the negative DIBL phenomenon. Figure 7 shows the I ds -V ds output characteristic of NC-JLFET for different T FE values at V gs = 0.5-0.7 V. As mentioned earlier, when V ds increases, V int decreases, which reduces the drain current. This exhibits a negative differential-resistance (NDR) characteristic as depicted in Fig. 7a. When V gs = 0.5 V, I ds and V ds have a positive correlation in the linear region. As V ds continues to increase, I ds decreases. This NDR effect can also be seen in the relationship between V int and V ds shown in Fig. 5. However, when V gs = 0.7 V, only a positive correlation exists between V int and V ds , so the NDR effect will not appear [see Fig. 7b]. In addition, as the negative DIBL is related to C FE , the NDR can be controlled by changing T FE . Despite the NDR, an NC-JLFET still provides a larger current than a traditional JLFET. It is worth mentioning that the simulation results of negative DIBL and NDR in our research are consistent with the results of [18]. Figure 8 shows the DIBL values of a JLFET and NC-JLFET for different N S/D . It can be clearly seen that as N S/D increases the DIBL effect becomes more serious for the JLFET. This can also be seen in the potential profile diagram. It can be observed from Fig. 9a that the barrier height is significantly reduced when N S/D = 5×10 19 cm −3 , resulting in a more serious DIBL effect. However, for the NC-JLFET, increasing N S/D has little impact on its DIBL, which can also be observed in the potential profile diagram. Figure 9b also shows that N S/D increased from 1 × 10 19 to 5 × 10 19 cm −3 and the barrier height shows a downward trend. Due to the negative capacitance effect, the negative DIBL phenomenon still occurs.  . It can be clearly seen that SS decreases with increasing T FE . This is mainly because as T FE increases, C FE will decrease, which will make C MOS more closely match C FE : According to Eq. 7 [23], the voltage amplification factor (A G ) increases due to the improved matching between the C MOS and C FE (|C FE | − C MOS > 0). The relationship between A G and SS is obtained by Eq. 8 [24], A G and SS have a negative correlation, so SS decreases with increasing T FE . The relationship between the ferroelectric capacitance (C FE ) and the ferroelectric material parameters (E c and P r ) is shown in Eq. 6 [11]. When P r (E c ) and T FE remain unchanged, C FE decreases as E c increases (P r decreases), and results in lower SS. The results obtained in the simulation also conform to this rule, as shown in Fig. 10a and b.

Conclusions
The electrical performance of a negative-capacitance double-gate junctionless transistor with additional source-drain doping determined by simulation analyses is presented in this paper. It was observed that the negative-capacitance effect and additional sourcedrain doping can increase the gate voltage and depletion capacitance, respectively, which makes the proposed NC-JLFET have higher I ON /I OFF and lower SS values. Then, the NDR and negative DIBL phenomenon are explained through the relationship between inter-nal voltage and gate voltage. In addition, the influence of ferroelectric parameters on the NC-JLFET with additional source-drain doping is explored and shown to have better performance when the proper coercive field, remnant polarization, and ferroelectric thickness are chosen. The additional source-drain doped NC-JLFET studied can achieve superior performance and meet the requirements of low-power IC applications in the future.

Conflict of Interest
The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in  the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the decision to publish the results.