A Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

In this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from low frequency to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed for RF-TSMC 0.18-μm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S21) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S11) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands.


Introduction
Over the past few years, various and new wireless communication standards have been developed to extend transceiver functionalities. The development of the IEEE 802.11a/b (2.4/5.2-GHz) standard has been widely used in Wireless Local Area Network (WLAN) applications due to support for high data rate communication (up to 54 Mb/s) and the wide range of its applications [1][2][3]. Therefore, the new trend in RF front-end receiver features a low noise amplifier (LNA) capable of receiv-ing multiband frequencies with a proper performance at each frequency band, as shown in Figure 1 [4].
The low noise amplifier (LNA) with dual bandwidth plays a critical role in the overall performance of the dual-band receiver. The design of the dual-band LNA (DB-LNA) includes some challenges such as high gain, low noise performance, low power dissipation, and proper input matching for both bands. Several approaches have been presented to implement the DB-LNAs with high performance operating at two different frequencies. The two single-band parallel LNAs configuration is one of the initial designs presented for DB-LNAs [5][6][7][8]. The measurement results show good performance at each frequency band at the expense of a larger chip area and higher power dissipation. The conventional methods use the switched inductors or switched capacitors in the input/output networks [9][10][11][12][13][14]. The structures consume low power, but generally degrade the gain and noise figure (NF) because of the insertion loss of their switches. Furthermore, LNA in such an approach can only operate with one band at a time. Another approach is to use a wideband LNA. Although this is a simple method for receiving multiple frequency bands simultaneously, the receiver sensitivity can be degraded due to the presence of unwanted signals in the wide frequency band. The most effective technique to achieve DB-LNA is to insert the notch filters in a wideband LNA [15][16][17][18][19][20]. Compared to the switchable LNAs, in this approach, the LNA supports simultaneous dual-band operations and consumes lower power. Hong et al. [17] used the cascode topology with gain boosting technique to achieve high gain and proper input matching. In addition, it employs the passive elements as bandpass/bandstop filters in the output network circuit to shape the frequency response, and to obtain a concurrent DB-LNA operating at 2.4/5.2GHz. Although this method results in a good performance in terms of linearity and power dissipation, it suffers from the unbalanced amplitude of the gain at the operating frequencies and weak roll-off in gain at the high band. Yu and Neihart [21] proposed a transformerbased multimode LNA using a reconfigurable multi-tap transformer as the gate inductor. The proposed LNA can dynamically achieve a single-band, or concurrent dual-band frequency response. However, it cannot provide high attenuation in the stopband and proper roll-off in gain at both bands in concurrent dual-band mode. In this paper, a two-stage concurrent DB-LNA in 0.18-μm CMOS technology is designed that operates at 2.4/5.2-GHz. The desired frequency bands are realized by using the LC network at the LNA output. The stagger tuning technique is also used to enhance the gain and provide a flat gain over the frequency band. Therefore, a concurrent DB-LNA with high balanced gain, proper roll-off in gain, and good input matching is obtained. The paper is organized as follows: Section 2 presents the design parameters of the proposed circuit, including the voltage gain, input impedance matching, noise figure, and band selection. In Section 3, the simulation results are presented and discussed. Finally, the conclusion is given in Section 4.

Design of proposed circuit
The schematic of the proposed DB-LNA is shown in Figure 2. It consists of two inverter-based stages using resistive shunt-shunt feedback along with an LC network connected at the circuit output. In each stage, the current-reused technique is utilized to achieve low power dissipation and improve gain performance. Since the DC currents of transistors M 2 and M 4 are reused by M 1 and M 3 , respectively, there is no requirement for additional driving currents for M 1 and M 3 . The resistive feedbacks are utilized to achieve simultaneous proper input matching and flat gain. They also provide a self-biased structure for the proposed DB-LNA. The series peaking inductors of L 3 and L 4 are inserted in the gate of M 1 and M 3 to extend the bandwidth and provide proper input matching. The LC network of L 1 , L 2 , and C 2 is implemented at the LNA output to realize the dual-band frequency response within the LNA frequency response. The proposed circuit can provide high gain and good input matching at the two passbands with high attenuation in the stopband. The capacitance of CC is employed to provide the DC bias isolation of the circuit.

Bandwidth and gain analysis
A wideband amplifier operating over low frequency to 5.2-GHz is first designed to obtain the main structure of the proposed DB-LNA. Then, the frequency response of the DB-LNA is shaped by inserting an LC network. So far, several topologies are reported to achieve the wideband LNA, such as common-gate [22,23] and shunt resistive feedback [3,24]. The common-gate (CG) configuration provides a wideband input impedance matching, high linearity, and good reverse isolation compared to the common-source (CS) configuration. Nevertheless, the CG configuration suffers from high NF, that is typically more than 3dB. Additionally, the feedback structure consumes more power. Using a modified inverter-based structure with shunt resistive feedback is an appropriate idea to improve the gain performance without additional power dissipation. Figure 3 shows a single modified inverter-based stage, which exhibits a relatively high flat gain over low frequency to 5.2-GHz. Higher gain is achieved by a second inverter-based LNA, which is connected in series with the first stage. However, the impedance mismatch between stages can result in ripples in the passbands, but using the stagger tuning technique results in flat gain over low frequency to 5.2-GHz. Figure 4 shows the proposed two-stage wideband LNA. The small-signal equivalent circuit of the proposed wideband LNA is shown in Figure 5. As can be seen, the feedback resistors of R 1 and R 2 are placed in parallel with the gate to drain capacitances (C gd ) to provide the wideband input matching. At the frequencies of interest, the impedances of the gate to drain capacitances are almost always much higher than the feedback resistor impedances that they are in parallel with. Therefore, C gd is neglected in the small-signal equivalent circuit of the proposed wideband LNA. In Figure 5, Z L1 = r o1 ||r o2 and Z L2 = r o3 ||r o4 , where r oi is the drain output resistance of M i . It is assumed that R 2 >>Z L2 for alleviating the loading effect of the second stage. By neglecting the gateto-drain capacitance (C gd ), the input impedance of the second stage (Z IN2 ) in case of ω<<ω T is obtained as follows: The overall voltage gain of the proposed wideband LNA is given by: where, A v1 and A v2 are the voltage gain of the first and the second stages, respectively. Based on the small-signal analysis, A v1 can be expressed as below: where gm represents the transconductance of the MOS transistor, and g mT1 =g m1 +g m2 is the overall transconductance of the first stage. Similarly, Av2 is obtained as follows: where g mT2 =g m3 +g m4 is the overall transconductance of the second stage. By assuming a small value for R 1 and high value for R 2 and regarding (2), A v,T is given as follows: By assuming R 1 /L 4 >5.2 GHz, A v,T can be simplified as: From (5) it can be seen that A v,T has four resonant frequencies ω p1,2 and ω z1,2 , that expressed by: From equation (6), it can be seen that the overall voltage gain is proportional to g mTi , and R 1 (Z L2 can be affected by load resistance). Since the input matching, power dissipation, and bandwidth limit the values of g mT1 and R 1 , the gain of the proposed wideband LNA can be adjusted by g mT2 . Moreover, the high band of the DB-LNA can be shaped by tuning ω p1 around 5.2-GHz. Figure 6 shows the overall frequency response of the proposed wideband LNA along with the frequency responses of the first and second stage. As can be seen, the proper roll-off in the upper-frequency response is achieved by setting ω z1 close to ω p1 .

Input impedance
Impedance matching over a wide band is one of the most challenging tasks in wideband LNA design. The input matching condition of the inverter-based LNA can be improved by applying the shunt-shunt resistive feedback and inserting an inductor in series with the gate of the NMOS transistor. According to equation (1) and assuming R 1 /L 4 >5.2-GHz, the input impedance of the proposed wideband LNA in case of ω<<ω T is expressed by: As can be seen, the input impedance is proportional to g mT1 , R 1 , and L 4 , thereby the trade-off between the gain and input matching can be reduced by only employing g mT1 for satisfying the input matching condition.

Noise figure
The noise performance of the wideband LNA is evaluated by assuming the thermal noise of the transistors and the resistors as the dominant noise sources, and the flicker noise is neglected. The loss of inductors is  neglected, and it is also assumed L 3 and L 4 resonate with the total capacitance at the input node of the first and the second stage, respectively. According to the mentioned conditions, the simplified circuit for noise calculation is derived, as shown in Figure 7.
The noise figure (NF) of the wideband LNA is given by: where A vs is the voltage gain from v S to v OUT , and regarding R IN ≈R 1 /2, it can be expressed by: where R o1 and R o2 represent the output resistance seen at the output nodes of the first and the second stage, respectively and they are given as: According to Figure 7, the total output noise is expressed as: (17) where α represents the ratio of g m to the zero-bias drain conductance gd0, and γ is the MOS transistor thermal noise coefficient. Figure 8 shows the contours of NF(g mT1 , R 1 ) in the case of I D3 =2 mA, R 2 =5 kΩ and V eff1 =V eff3 =0.2 V. As shown in Figure 8, there is a tradeoff between R 1 and g mT1 at a specific NF, and the proper NF can be achieved by choosing higher values for R 1 and g mT1 . Additionally, R 1 and g mT1 are limited by input matching, and thereby, a lower NF can be achieved regarding proper input matching and power dissipation.

LC network
As mentioned earlier, the circuit design starts with the design of a wideband LNA that exhibits a high flat gain over the low frequency to f 2 =5.2-GHz. It should be noted f 2 is defined by f p1 . It is assumed that the receiver receives two frequency bands concurrently without using switches. Therefore, concurrent DB-LNA is a development based on a multiband theory to achieve dualband characteristics. For this purpose, an LC network is inserted in the LNA output to achieve the requirements with minimum effect on the gain, NF, and input matching. The proposed LC network determines the low band of the concurrent DB-LNA and enhances the spurious frequency rejection at the low frequency.  Additionally, the frequency calibration method can be realized by using a varactor to tune the frequency shift due to the process variation. Figure 10 shows the frequency response of the proposed DB-LNA determined by the LC network.

Simulation results
The proposed concurrent DB-LNA is designed and simulated using Cadence Spectre-RF with 0.18 μm CMOS technology. The post-layout simulation results are reported in the paper, which take into account layout parasitic capacitances. The power supply of 1.5 V is used, and the minimum channel length is considered for all transistors. The first stage is designed to achieve moderate gain, low NF, and proper input matching over the lower frequencies to 5.2-GHz. Transistors M 1 and M 2 have the same width of 165 μm, while M 1 is biased at gate-source voltage (v gs1 ) of 0.64 V, thereby g m1 = 60 mA/V and g m2 =25 mA/V. A higher g mT1 value reduces the NF, but increases the power dissipation and degrades the input matching. According to (7) and (9), the ω z1 is located at about 1.85ω p1 , thereby providing a proper roll-off at the upper-frequency band. The second stage enhances the gain and obtains a flat gain over a wide frequency band. For this purpose, the transistors M 3 and M 4 are designed to have g m3 =90 mA/V and g m4 =10 mA/V, while M 3 is biased at v gs3 =0.54 V with the total width of 310 μm, and M 4 has the width of 50 μm. The transistor dimensions chosen above and, according to (11) and (13), lead to L 3 =4.2 nH, L 4 = 2 nH, R 1 =135 Ω, and R 2 =1.5 kΩ. Figure 11 shows the simulated power gains of the two separate stages and the proposed wideband LNA operating over the low frequencies to 5.2-GHz.
As shown in Figure 6, if the resonant frequencies of A v1 and A v2 are properly optimized, such as placing ω p2 at approximately 4-GHz and ω p1 at 5-GHz while keeping reasonable input-matching, a wideband flat power gain is expected. The dual-band gain response is achieved when the LC network is inserted at the output of the wideband LNA. Resonating at 3.8-GHz, L 2 and C 2 result in a very low output impedance. C 2 is chosen to be about 1.4 pF, while L 2 is adjusted about 1.5 nH. From (21), it can be seen that the low band operation of f 1 =2.4-GHz is achieved with L 1 =1.6 nH. Table 1 lists the optimized component values of the concurrent DB-LNA and the bias current of transistors. 1500 Bias (V) V DD 1.5 Figure 12 shows the layout of the proposed DB-LNA, occupying 0.55 mm×0.48 mm chip area, excluding the pads.
The post-layout simulated power gain (S 21 ) and input return loss (S 11 ) of the concurrent DB-LNA are shown in Figure 13 and Figure 14, respectively. As shown in Figure 13, the balanced amplitude of the gain at the oper- Figure 11: The simulated S 21 of the proposed LNA.
ating frequencies of 2.4-GHz and 5.2-GHz is achieved by choosing L 1 =1.6 nH and L 2 =1.5 nH. Figure 14 shows the value of g mT1 that determines the input matching range. As shown in Figure 14, the simultaneous dualband input matching smaller than -10 dB is achieved by choosing the g mT1 smaller than 85 mA/V. However, the smaller values of g mT1 can potentially achieve a higher noise figure up to 2 dB and yield a substantially lower gain.   The IIP3 is carried out by applying a two-tone test with 4-MHz frequency spacing. As shown in Figure 16, the post-simulated IIP3s are -6 dBm and -11 dBm at 2.4-GHz and 5.2-GHz, respectively. Figure 17 shows the stability factors based on the Sparameters to consider the stability of the proposed DB-LNA. The necessary and sufficient conditions for unconditional stability are expressed as follows:  As shown in Figure 17, the concurrent DB-LNA satisfies the conditions for unconditional stability at both frequency bands.
Monte Carlo analysis is carried out on the proposed DB-LNA to evaluate the effects of components mismatches on performance parameters such as S 21 , NF, and S 11 . In Monte Carlo simulation with 1000 iterations, a 2% mismatch with Gaussian distribution for all circuit components is considered. As shown in Figures 18 and 19  As seen in Figures 18 and 19, the Monte Carlo simulation results confirm the low sensitivity of the proposed DB-LNA to process variations at both frequency bands. The process corner cases and temperature variation are simulated at the operating frequencies, and the results are listed in Table 2. The proposed DB-LNA is also simulated over the power supply variation, and the results are listed in Table 3. Table 4 has compares the performance of the proposed DB-LNA with similar reported works. A figure of merit (FoM) in both bands, which allows comparison between the concurrent DB-LNAs, is defined as follows: where f 1 and f 2 represent the centre frequencies of the low band and the high band of the concurrent DB-LNA, respectively. According to Table 4, the DB-LNA in (Roobert & Rani [25]) presents a high power gain and low NF at both bands. However, its operating frequencies are lower than those of the proposed DB-LNA. Moreover, (Neihart et al., [26]) achieves a low power DB-LNA. However, it suffers from the unbalanced amplitude of the gain at the operating frequencies. As seen in Table 4, the proposed circuit exhibits high and balanced amplitude of the gain and excellent input matching, moderate linearity, and power dissipation.

Conclusion
This

Conflict of interest
The authors have no affiliation with any organization with a direct or indirect financial interest in the subject matter discussed in the manuscript.