Design of a Low Power and High-Efficiency Charge Pump Circuit for RFID Transponder EEPROM

The charge pump (CP) circuit is an essential part of a radio frequency identification electrically-erasable-programmableread-only memory (RFID-EEPROM). A CP circuit generates a boosted output voltage that is greater than the power supply voltage. However, the performance of the diode configured CP circuits is strongly affected by the extra power dissipation and the parasitic capacitance. The parasitic capacitors of the CP circuit are also responsible for increased power consumption. In this research, an improved CP circuit is designed for achieving higher output voltage gain by reducing the parasitic capacitances. Moreover, the proposed course consumes less power, which makes it more suitable for low power applications like RFID transponder. The proposed CP circuit is using the internal boosted voltage for backward control where active controls are applied to the charge transfer switch (CTS) to eradicate the reverse charge sharing trends. Simulated results showed that by using 1 pF pumping capacitor to drive the capacitive output load, the proposed circuit generates 9.56 V under 1.2 V power supply. In comparison with other research, works, this CP circuit consumes less power (only 15.26 μW), which is lower than previous research works. Moreover, the proposed CTS CP circuit can operate with the efficiency of 79.3%, which is found higher compared to other research works. Thus, the proposed design will be an essential module for low power applications like RFID transponder EEPROM.


Introduction
A typical RFID transponder is known as data carrying devices in RFID systems. RFID transponder can be embedded in objects like electronic devices, luggage, pets, or human being for identification. The RFID transponder is a chip or small circuit board coupled to an antenna [1]. A typical RFID chip contains mainly three blocks, such as analogue, logic, and memory blocks. To store information in the readerless RFID transponder, a small amount of NVM should be embedded [2] Transponder memory can contain read-only memory (ROM), Random Access Memory (RAM), non-volatile memory as EEPROM, flash memory, etc. and data buffers subjected to the device functionality [3]- [4].
Different types of memories exist in the market. Among them embedded NVM such as EEPROM is mostly used as tag memory in RFID, SoC, and FPGA systems. However, the prerequisites, additional masks, and fabrication steps made EEPROM and Flash memory highly expensive compared to a standard CMOS logic process. Many researchers wanted to develop EEPROM in a traditional CMOS logic process as it has the advantages of low cost and low power [5]- [8].
However, the maintenance and endurance features are inadequate due to the NMOS tunnelling junction or the single-ended memory cell architecture with a too-thin oxide [5]- [6]. It has a large area/bit and consumes much power as each bit cell contains its high voltage switch [7]- [8]. To generate the high voltages, an internal highvoltage generator circuit such as voltage doublers or CP circuit is required [9].
Currently, low-voltage and small size DC-DC converters are widely required for mixed-mode circuit schemes. To transform an input voltage from low to high with either a positive or reverse polarity, the CP circuit can be the vital element to encounter the demands [10]. In the CP circuit, capacitors are needed to store the energy of any devices instead of magnetic constituents. The capacitors required by the CP circuit can be small enough to be fabricated in IC. For low-power designs, CP circuits are needed to generate dc voltages higher than the power supply (VDD) or lower than the ground voltage (GND) of the memory chip. With the features of high-energy efficiency, small space, low power dissipation, and low current drivability, the CP circuit is chosen by the researcher as the compulsory module in EEPROM. Commonly, it is applied to the EEPROM in RFID transponder, DC-DC converters, and power supervision chips to write or to erase the floating-gate devices [11][12][13].
Dickson established the most widespread CP circuit in 1976, where the CP circuit used the diode-connected NMOS arrangement as a charge transfer device instead of switches [14] (Dickson, 1976). However, power efficiency and voltage gain in each stage are very low in the diode-connected CP circuit due to the body effect. Several types of research have been made to enhance the performance of the CP circuit [15][16]. Yan et al. have considered a CP with additional devices, which suffered from more power consumption for a lower current load [15]. Liu et al. proposed a CP with charge transfer switches (CTS) and parasitic capacitors to solve the problem of body effect. Besides, the CP circuit used the next pumping voltages to switch each CTSs [16]. However, the enlarged parasitic capacitance at every pumping stage decreases the pumping efficiency or the voltage gain. In 2009, Wang et al. also designed a CP circuit with the backward. They forwarded the CTS controlling method to recover the efficiency, to eradicate the body effect, and to escalate the voltage gain [17]. Nevertheless, the pumping efficiency or voltage gain is still lower with the PMOS switch in the output stage.
In this research, an improved CP circuit using CTS with reduced parasitic capacitance is described. The designed CP circuit is capable of reducing power consumption and increased voltage efficiency, which is compatible with the RFID transponder EEPROM. Silterra 0.13 μm CMOS process is utilized to design and verify the enhanced CP circuit. The comparative study proves that the proposed design decreased the parasitic capacitance, increased the pumping efficiency, and cut down the power consumption compared Liu et al. and Wang et al. 's CP circuit.

Materials and methods
In this research, CTS is the most widely used CP design method, which has been used by many researchers in their study. In this scheme, the dynamic charge transfer scheme in each step is the key to enhancing the boosted charge from the lower supply voltage. Most of the previous researchers included both the NMOS and PMOS transistors to implement the diode configuration in CMOS, where PMOS transistors created a large substrate current in each step of the charge transfer process, which eventually increased the power dissipation of the overall design. Therefore, in this research, a novel CTS-based CP circuit is proposed, where all the PMOS transistors are excluded, and NMOS transistors are utilized in all stages. This reduces the substrate current or in another term, the power dissipation of the overall circuit. The schematic diagram of the proposed CTS CP circuit is shown in Figure 1. In this research, Silterra 0.13 μm CMOS process is used to design the schematic of the proposed CP circuit. From Figure 1, it is shown that one diode-configured MOSFET MD1 is utilized in this design to initiate the voltage from the supply voltage VDD to start the charge transfer process from one stage to another, whereas, another MOSFET MD2 is connected with the output stage of the circuit. On the other hand, transistors (MS1-MS9) are required to control the CTS and to transmit the boosted charges from the first stage to last using the backward charge transfer scheme. As all the CTS switches from MS1-MS9 does not entirely turn "OFF" during this transfer process, additional controlling transistors MN1 to MN9 and MP1 to MP9 are added in this design. In this research, when the clock signal CLK is in a high state, and the anti-phase clock signal CLKB is in a low condition, the gate of transistor MS2 is turned ON at the time of the charge pump process, which holds the amplitude of VDD as the pass transistor MN2 is switched OFF and MP2 is switched ON. Therefore, transistor MS2 has the value of VDD to node 2. On the other hand, when CLK is in a low state, and CLKB is in a high condition, the pass transistor MN2 is turned ON, and MP2 is turned OFF. Therefore, the gate voltage of MS2 becomes zero, which turns OFF the MS2 transistor entirely and the entire CP circuit feedbacks the charges from stage one to the next. In this design process, the total performance of the circuit closely depends on the sizing of the transistors. In this topology, zero V th MOS-FETs help to overcome the threshold voltage drop at each stage, which helps to boost the pumping process of this scheme. Usually, the amplitude of the V clk is same as V DD, in this scheme. Thus, the voltage variation and the voltage fluctuation of each pumping node can be expressed as, where V CLK is the voltage amplitude of the clock signals, C pump is the pumping capacitance, C par is the parasitic capacitance of each pumping node, I o is output current, and f is the clock frequency. If I o is small enough, and C pump is large enough, I o can be ignored from equation (2). Hence, the output voltage of the N-stage CP circuit can be expressed as where V D is the cut-in voltage of the pn-junction diode and N is the number of the stages taking part in pumping. The ripple voltage is defined as: where, C out is the load capacitance, which is ignored to calculate the ripple voltage of the proposed CP circuit. The number of stages determines the power efficiency because of V out and VDD, which are determined by the specific CMOS process [18].
Die layout of the proposed CP circuit with I/O padded structure is shown in Figure 2, where the CP circuit without I/O pad occupies only a small area of 224.2 μm × 73.2 μm. During the design process, all transistors and capacitors are placed in a manner that reduces the mismatch and parasitic capacitance. Figure 2 shows the chip layout of the proposed CP circuit with I/O pads.

Results and discussions
The operating temperature was set to 27 o C for the CTS CP circuit and the ELDOSPICE simulator (Mentor Graphics) was used within Silterra 0.13 μm CMOS process. VDD for simulating the outputs is set to 1.2 V. The simulated behaviour of the CTS CP circuit is illustrated in Figure 3. Figure 3 shows the simulated output voltage waveform of the proposed eight-stage CP circuit with 2pF pumping capacitors. Ideally, the output voltage of the designed eight-stage CP circuit with power supply voltage VDD= 1.2 V should be as high as 9.6 V (1.2 x 8 = 9.6 V). However, the output voltage of the proposed CP circuit is decreased due to some parasitic capacitances at every pumping node and the loading of the output current. Therefore, the simulated output voltage of the proposed CP circuit is achieved V out = 9.56 V. In this proposed design, both the clock signals (CLK and CLKB) amplitude is set to 1.2 V as same as the supply voltage. The circuit is simulated using 10.2 MHz clock frequency to observe the pumping performance of the proposed CP circuit. If the clock frequency is increased, the charge is transferred over a fixed time interval from one step to another in a faster way, which also increases the output voltage. At 50 MHz clock frequency, the proposed CP circuit exhibited the best performance. In this proposed design, increasing the clock frequency raises the output voltage gain, but incomplete charge transferring occurs if the circuit operates above 50 MHz clock frequency.
On the other hand, the proposed CP circuit is simulated for all 45 corners. In this research, 3 Vcc (1.1 V, 1.2 V, and 1.3 V), three temperatures (-40 0 C, 27 0 C and 125 0 C), and five corners are examined, as shown in Figure 4. This corner analysis and process variation tests ensure the proposed CTS based CP circuit function correctly within manufacturing tolerances, which is compulsory in CMOS design. The corner test results revealed that the proposed CP circuit could function properly at different corners of VDD and temperature.
The proposed design of the CP circuit achieved output voltage V out = 9.56 V, which is higher than recently published research works, as shown in Figure 5. The simulated results discovered that [16] and [19] CP circuits achieved poor V out due to threshold voltage loss and high parasitic capacitances in every node of the pumping stages. Conversely, to compare the simulated results with recently published research works, this proposed design is tested with different supply voltages, which is shown in Figure 5. From this comparison, it is evident that this novel CP circuit performed better than other research works for all the supply voltage values from 1.2 V to 2.4 V.
On the other hand, the comparison results of the load current against different VDD among the proposed CP circuit, [16] and [19] are shown in Figure 6. From Figure 6, it is observed that the proposed CP circuit can operate successfully with a higher load current under different supply voltage ranges from 1.2 V to 2.4 V. The higher the load current a CP can drive the better its performance, so from Figure 6, it can be said that the proposed CP circuit's performance is better compared to [16] and [19] with higher load current.
Moreover, in this proposed design, a small number of pumping capacitors are utilized the parasitic capacitors (C par ) are removed as shown in [16], which helps to trim down the parasitic capacitance effect and leads to reduced load current against different supply volt- age ranges 1.2≤<VDD≤2.4. The proposed CP circuit attained a higher output voltage V out at a low power supply voltage as this proposed topology can reduce the parasitic capacitance effect. Moreover, by using the backward control process with the dynamic CTS scheme, the triple well MOSFETs are turned on/off successfully. This proposed design CP circuit achieved lower power dissipation compared to recently published research works within a supply voltage ranges from 1.2 V to 2.4 V. At VDD = 1.2 V the power consumption of CP circuit from [19] was 51.57 μW. At the same voltage level, the CP circuit from [16] consumed 171.25 μW.
On the other hand, the proposed CP circuit dissipates only 15.26 μW, which is much lower than the recently published research works. The power efficiency at VDD= 1.2 V is calculated using equation (5) for [16], [19] and the proposed CP circuit with a different number of stages, which is shown in Figure 7. From Figure 7 it is found that for a different number of steps the proposed CP circuit can produce higher pumping efficiency up to 79.3% at 10.2 MHz using 2 pF pumping capacitances, which are much higher compared to [16] and [19]. The size of each pumping capacitor of the CP circuit must be equal to get better comparison results. Conse-quently, every pumping capacitors of the proposed CP circuit, [16] and [19] circuits was set to 2 pF, 1 pF, and 0.1 pF, respectively. For HVG compatible CP circuit, power efficiency can be expressed as, The number of stages only determines the power efficiency of V out and VDD is fixed by the application [18]. Compared to the initial Dickson CP circuit, when the diodes have zero Vt, the power efficiency is improved by VDD/ (VDD -V t ) using equation (5). Of course, the result is higher when VDD is low. The power efficiency at VDD= 1.2 V is measured for [16] and [19]. The proposed CP circuit with a different number of stages is, as shown in Figure 6. Table 1 summarizes the comparison studies among the proposed CP circuits along with the recently published research works.
Compared to all recently published research works, the proposed CP circuit has achieved the highest output voltage of 9.56 V under a supply voltage of 1.2 V, as shown in Table 1. In this design, the W/Ls of MD1 and MD2 were increased and the W/Ls of MS1-MS9 decreased, which helped to produce a higher output voltage, which is better than all the previous research outputs. However, [20] is made slightly higher output than this research work, which is achieved due to the higher supply voltage compared to this research work. Moreover, the proposed design achieved the highest pumping efficiency of 79.3%, which is better than [19,[21][22]. The result is achievable, as it has a smaller number of parasitic capacitances to turn out higher efficiency under low supply voltages. The pass transistors (MNs and MPs) were used in this design to prevent voltage loss and reverse the charge-sharing mechanism, which also improves the process of charge transfer and boosts the output voltage. In this research, the frequency was set to 10.2 MHz for the two anti-phase clock signals of the proposed CP circuit, which met the required specifications of the HVG.
Moreover, the designed CP circuit can perform up to 50 MHz, which makes the proposed design superior to [16,20,[21][22]. In terms of accessibility. From the comparison table, it is also found that the proposed design has the lowest power dissipation of only 15.26 μW with eight stages of pumping capacitors, which is better than [16,19,21]. The proposed CP circuit used the triple well NMOS switch to control the CTSs dynamically instead of diode-configured switches in all stages. Hence, no substrate current is formed throughout the dynamic control process. Using PMOS transistors results in a substrate current at each step during Figure 6: Comparison of load current against supply voltages among [16], [19] and this work under 1.2 ≤<VDD≤2.4. the charge transfer process. As a result, the proposed CP circuit dissipated lower power with better reliability compared to recently published research works.

Conclusions
An enhanced CP circuit is illustrated in this research by using the four-stage CTS scheme to move the charges directly with improved pumping efficiency. Design and prefabrication simulation of the CP circuit was done with only 15.26 μW power dissipation, which was lower compared to recently published research works. 9.56 V of boosted internal supply voltage was obtained and 79.3 % pumping efficiency was achieved by decreasing the parasitic capacitance effects. Again, these were the highest value among compared research works. From these analyses, it is evident that the designed CP circuit can perform in low voltage devices with lower parasitic capacitances, which results in lower power consumption compared to previous designs.