A 3.0 – 3.6 GHz LC-VCO with ETSPC Frequency Divider in 0.18-micron CMOS technology

Vytautas Macaitis, Marijan Jurgo, Jevgenij Charlamov, Vaidotas Barzdenas

Abstract


This paper proposes the design, implementation, and measurement of a fully integrated voltage controlled oscillator (VCO) and frequency divider for multi-band transceivers in 0.18-micron IBM 7RF CMOS technology. The VCO is composed of a cross-coupled NMOS transistor-pair and LC tank as a core circuit and 4-bit digitally-switched capacitor block with linearly varying varactors for enhancement of the wide oscillation frequency bandwidth. A design of frequency divider is based on extended true-single-phase-clock (ETSPC) flip-flops with divide values ranging from 2 to 256 for very wide output frequency range. The measured results indicate that the LC-VCO frequency range is from 3.02 GHz to 3.55 GHz, and the phase noise is ‑108.89 dBc/Hz at 1 MHz offset from 3.55 GHz carrier. The power consumption of the LC-VCO with ETSPC frequency divider including all the buffers and other circuits is about 212 mW for 2.49 dBm of output power. The active area of the test chip occupies only 0.65×0.65 mm2 and the whole chip size including the ESD protection circuits and pads is 1.5×1.5 mm2.

Keywords


Frequency divider; integrated circuits (IC); phase noise; transceivers; tuning range; voltage controlled oscillator (VCO);

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References


B. Razavi, “Multi-decade carrier generation for cognitive radios”, in IEEE Symposium on VLSI Circuits, June 2009, pp. 120-121.

A. Ford, T. Johnson, M. Linder, D. Aberg “A Comparative Study of CMOS LC VCO Topologies for Wide-Band Multi-Standard Transceivers” in IEEE Mid-west Symposium on Circuits and Systems, MWSCAS 2004, vol. 3, pp. 17–20. [Online]. Available: http://dx.doi.org.sci-hub.org/10.1109/MWSCAS.2004.1354280

B. Razavi, K. F. Lee, R. H. Yan, “Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS”, IEEE Journal of Solid-State Circuits, vol. 30, no. 2, pp. 101-109, Feb. 1995. [Online]. Available: http://dx.doi.org/ 10.1109/4.341736

H. Wang, “A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 μm CMOS”, in Proc, of IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2000, pp. 196-197.

Z. Deng, A. M. Niknejad, “The Speed–Power Trade–Off in the Design of CMOS True–Single–Phase–Clock Divider”, IEEE Journal of Solid–State Circuits, vol. 45, no. 11, pp. 2457–2465, 2010. [Online]. Available: http://dx.doi.org/10.1109/JSSC.2010.2074290

M. Moghavvemi, A. Attaran, “Performance Review of High-Quality-Factor, Low-Noise, and Wideband Radio-Frequency LC-VCO for Wireless Communication”, IEEE Microwave Magazine, vol. 12, no. 4, pp. 130–146, 2011. [Online]. Available: http://dx.doi.org/10.1109/ MMM.2011.940602

E. Kytonaki, Y. Papananos, “A Low-Voltage Differentially Tuned Current-Adjusted 5.5-GHz Quadrature VCO in 65-nm CMOS Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 5, pp. 254–258, 2011. [Online]. Available: http://dx.doi.org/10.1109/TCSII.2011.2149010

P. Andreani, K. Kozmin, P. Sandrup, “A transmitter CMOS VCO for WCDMA/EDGE” in IEEE European Solid-State Circuits Conference, ESSCIRC 2010, Sep. 2010, pp. 146–149. [Online]. Available: http://dx.doi.org/10.1109/ESSCIRC.2010. 5619854

V. Mačaitis, V. Barzdėnas, R. Navickas, “Design of 4.48–5.89 GHz LC-VCO in 65 nm RF CMOS Technology”, Electronics and electrical engineering. Kaunas: Technologija, vol. 20, no. 2, pp. 44-47, 2014. ISSN 1392-1215. Vol 20, no.2 (2014), p. 44-47. [Online]. Available: http://dx.doi.org/10.5755/j01.eee.20.2.6383

V. Mačaitis, V. Barzdėnas, “Design and Investigation of 65 nm RF CMOS technology LC-VCOs”, Science-Future of Lithuania, vol. 6, no. 2, pp. 198–201, 2014. [Online]. Available: http://dx.doi.org/ 10.3846/mla.2014.029

Jiawei Hu, Zhiqun Li, Zhigong Wang, “A 0.5-V 4.8GHz CMOS LC VCO with Wide Tuning Range”, in Proceedings of 2010 IEEE International Conference on Ultra-Wideband, ICUWB 2010, Sep. 2010, pp. 1–4. [Online]. Available: http://dx.doi.org/10.1109/ ICUWB.2010.5615771

A. D. Berny, A. M. Niknejad, R. G. Meyer, “A wideband low-phase-noise CMOS VCO”, in IEEE Custom Integrated Circuits Conference, 2003 Proceedings, Sep. 2003, pp. 555-558. [Online]. Available: http://dx.doi.org/10.1109/CICC.2003.1249459

Z. Deng, A. M. Niknejad, “The Speed–Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Divider”, IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2457-2465, Nov. 2010. [Online]. Available: http://dx.doi.org/10.1109/JSSC.2010.2074290


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