Towards smaller single-point failure-resilient analog circuits by use of a genetic algorithm

Žiga Rojec

Abstract


Failure-resilient analog circuits are difficult to design, but artificial intelligence can help crawl the topology solution space. Us-ing evolutionary computation-based topology synthesis we evolve analog arcus tangent computational circuits, resilient to any rectifying diode or resistor high-impedance single failure or removal. We encode analog circuit topologies as individuals with an upper-triangular incident matrix. Circuits are evolved using a combined technique utilizing parts of NSGA-II and PSADE, based on a special three-dimensional robustness function. We show that topology size for a failure-resilient circuit can be classes smaller than hand-made component-redundancy-based solutions. Our best failure-resilient topology comprises six diodes, three resistors, and a voltage offset source.

Keywords


analog circuits; analog circuit synthesis; circuit optimization; failure-resilience; circuit robustness

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References


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DOI: https://doi.org/10.33180/InfMIDEM2023.205

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