A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

Mehran Nohtanipour, Mohammad Hossein Maghami, Mehdi Radmehr


This paper presents a new placement and routing method for layout generation of CMOS operational amplifiers (op-amps). Both circuit sizing and layout generation stages are performed automatically. In the proposed method, layout effects are considered during the layout generation. Layout parasitics and geometry information are extracted from a new automated layout generator. In this method, the multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as an optimization algorithm. In order to verify the performance of the proposed method, the design of three-stage operational amplifier (op-amp) and two-stage class-AB operational trans-conductance amplifier (OTA) in a 0.18µm process CMOS technology with 1.8 V supply voltage are presented. The simulation results indicate the efficiency of the proposed analog layout generation method.


Analog layout generation; Circuit sizing; Automated placement and routing; MOEA/D; Three-stage operational amplifier.

Full Text:



Y. Gua, et al., Rapid and accurate method for resiz-ing CMOS operational amplifiers, Analog Integrat-ed Circuits and Signal Processing, 99 (2019), 447-454.https://doi.org/10.1007/s10470-019-01428-8

R. Martins, et al., Many-Objective Sizing Optimiza-tion of a Class-C/D VCO for Ultralow-Power IoT and Ultra low-Phase-Noise Cellular Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (2019), 69-82. http://doi.org/10.1109/TVLSI.2018.2872410

S. Park, S. Raman, Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (2019), 679 – 690. https://doi.org/10.1109/TVLSI.2018.2888593

D. Martev, S. Hampel, U. Schlichtmann, Automat-ed Phase-Noise-Aware Design of RF Clock Distribu-tion Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (2018), 2395-2405. https://doi.org/10.1109/TVLSI.2018.2864316

W. Lyu, et al., An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, 65 (2018), 1954–1967.

S. M. Anisheh, C. Dadkhah, A two-stage method for optimizing the parameters of CMOS operational amplifiers based on evolutionary algorithm, Inter-national Journal on Computer Science and Engineer-ing, 14 (2017), 1-10.

N. Khalil, et al., An intelligent technique for gener-ating equivalent gyrator circuits using Genetic Al-gorithm, Microelectronics Journal, 46 (2015), 1060–1068. https://doi.org/10.1016/j.mejo.2015.09.004

M. H. Maghami, F. Inanlou, R. Lotfi, Simulation-Equation-Based Methodology for Design of CMOS Amplifiers Using Geometric Programming, Proc. of 15th IEEE International Conference on Electronics, Circuits and Systems (2008), 360-363. https://doi.org/10.1109/ICECS.2008.4674865

H-J. Chang, et al., Layout-aware Analog Synthesis Environment with Yield Consideration, Proc. of 16th International Symposium on Quality Electronic De-sign (2015), 589-593.

R. Martins, N. Lourenco, N. Horta, LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits‚ IEEE Transactions on Computer-Aided De-sign of Integrated Circuits and System, 32 (2013), 1641-1654. https://doi.org/10.1109/TCAD.2013.2269050

E. Yilmaz, G., Dündar, Analog Layout Generator for CMOS Circuits, IEEE Transactions on Computer-Aided Design, 28 (2009), 32-45. https://doi.org/10.1109/TCAD.2008.2009137

A. Agarwal, R. Vemuri, Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners, Proc. of International Conference on Computer De-sign (2005), 1-6. https://doi.ieeecomputersociety.org/10.1109/ICCD.2005.68

A. Ferreira, et al., Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach, Proc. of 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (2016), 1-4. https://doi.org/10.1109/SMACD.2016.7520740

N. Lourenco, et al., AIDA: Layout-aware analog cir-cuit-level sizing with in-loop layout generation, In-tegration, the VLSI Journal, 55 (2016), 316–329. https://doi.org/10.1016/j.vlsi.2016.04.009

A. Toro-Frías, et al., Layout-aware pareto fronts of electronic circuits, Proc. of European Conference on Circuit Theory and Design (2011), 345-348. https://doi.org/10.1109/ECCTD.2011.6043357

T. Liao, L. Zhang, Parasitic-aware GP-based many-objective sizing methodology for analog and RF in-tegrated circuits‚ Proc. of Asia and South Pacific Design Automation Conference (2017), 475-180.

P. Vancorenland, et al., A layout-aware synthesis methodology for RF circuits, Proc. of IEEE/ACM ICCAD (2001), 358–362.

S. Youssef, et al., A Python-Based Layout-Aware Analog Design Methodology for Nanometric Tech-nologies, Proc. of IEEE 6th Int. IDT (2011), 62-67.

Y-C. Liao, et al., LASER: layout-aware analog syn-thesis environment on laker, Proc. of 23rd ACM GLSVLSI (2013), 107–112. https://doi.org/10.1145/2483028.2483071

R. Castro-Lopez, et al., An Integrated Layout-Synthesis Approach for Analog ICs, IEEE Transac-tions on Computer Aided Design, 27 (2008), 1179-1189. https://doi.org/10.1109/TCAD.2008.923417

G. Berkol, et al. A Two-Step Layout-in-the-loop De-sign Automation Tool, Proc. of IEEE 13th NEWCAS (2015), 1-4.

A. Agarwal, et al., Fast and accurate parasitic ca-pacitance models for layout-aware synthesis of an-alog circuits, Proc. of 41st Conference on Design Au-tomation (2004), 145–150. https://doi.org/10.1145/996566.996610

K. Choi, D. Allstot, S. Kiaei, Parasitic-aware synthe-sis of RF CMOS switching power amplifiers, Proc. of IEEE International Symposium on Circuits and Systems (2002), 269–272.

G. Zhang. et al., A synthesis flow toward fast para-sitic closure for radio-frequency integrated circuits, Proc. of Design Automation Conference (2004), 155–158. https://doi.org/10.1145/996566.996612

M. Ranjan, et al., Fast, layout-inclusive analog cir-cuit synthesis using precompiled parasitic-aware symbolic performance models‚ Proc. of Des., Au-tom. Test Eur. Conf. (2004), 604–609.

A. Ahmed, L. Zhang, Fast parasitic-aware synthesis methodology for high-performance analog circuits‚ Proc. of IEEE International Symposium on Circuits and Systems (2012), 2155-2158. https://doi.org/10.1109/ISCAS.2012.6271714

S. M. Anisheh, H. Shamsi, Placement and Routing Method for Analogue Layout Generation Using Modified Cuckoo Optimization Algorithm, IET Cir-cuits Devices & Systems, 12 (2018), 532-541. https://doi.org/10.1049/iet-cds.2017.0111

Y. Yan Tan, et al., MOEA/D+uniform design: A new version of MOEA/D for optimization problems with many objectives, Computers & Operations Re-search, 40 (2013), 1648-1660. https://doi.org/10.1016/j.cor.2012.01.001

I. Giagkiozis, et al., Generalized Decomposition and Cross Entropy Methods for Many-Objective Opti-mization, Information Science, 282 (2014), 363-387.

Q. Zhang, H. Li, MOEA/D: A Multiobjective Evolu-tionary Algorithm Based on Decomposition, IEEE Transactions on Evolutionary Computation, 11 (2007), 712-731. https://doi.org/10.1109/TEVC.2007.892759

Y. Jin, T. Okabe, and B. Sendho, Adapting Weighted Aggregation for Multiobjective Evolution Strate-gies, International Conference on Evolutionary Mul-ti-Criterion Optimization (2001), 96-110.

H. E. Graeb, Analog Layout Synthesis‚ New York, NY, USA: Springer, 2011.

L. Zhang, Z. Liu, Directly performance-constrained template-based layout retargeting and optimiza-tion for analog integrated circuits‚ Integration, the VLSI journal, 44 (2011), 1–11. https://doi.org/10.1016/j.vlsi.2010.09.003

S. M. Anisheh, H. Shamsi, Two-stage class-AB OTA with enhanced DC gain and slew rate‚ Interna-tional Journal of Electronics Letters, 5 (2017), 438-448. https://doi.org/10.1080/21681724.2016.1253780

S. M. Anisheh, H. Shamsi, M. Mirhassani, Positive Feedback Technique and Split-Length Transistors for DC-Gain Enhancement of Two Stage Op-Amps, IET Circuits Devices & Systems, 11 (2017), 605-612. https://doi.org/10.1049/iet-cds.2016.0416

S. M. Anisheh, H. Abbasizadeh,, H. Shamsi, C. Dad-khah, K. Y. Lee, 84 dB DC-gain two-stage class-AB OTA‚ IET Circuits Devices & Systems, 13 (2019), 614-621. https://doi.org/10.1049/iet-cds.2018.5038

R. Nguyen, B. Murmann, The design of fast-settling three-stage amplifiers using the open-loop damp-ing factor as a design parameter, IEEE Transactions on Circuits and Systems-I: Regular Papers, 57 (2010), 1244-1254. https://doi.org/10.1109/TCSI.2009.2031763

DOI: https://doi.org/10.33180/InfMIDEM2021.304


  • There are currently no refbacks.

Copyright (c) 2015 Mehran Nohtanipour, Mohammad Hossein Maghami, Mehdi Radmehr

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.