Design and Optimization of Multiple-Channel DDSB Op-Amp for SC Integrator Using FinFET Technology

Firat KACAR

Abstract


This paper presents the design and optimization of a parametric multiple-channel Double Dynamic Switching Biased Complementary Folded-Cascode Amplifier with switched capacitor integrator application in 32nm FinFET technology. The LTspice simulations demonstrate that the amplifier can attain an open-loop DC gain of 44.8dB, and a phase margin of about 87.8° with ±0.5V supply voltages. Moreover, the amplifier power consumption is measured 246µW including bias circuitry and a Gain-Bandwidth Product (GBW) of 77.45MHz under a 5pF load capacitor. The circuit's stability enables it to offer diverse design capabilities tailored to specific application needs. This novel design is capable of reducing supply voltages and power dissipation.


Keywords


32nm FinFET Technology; Complementary Folded-Cascode Amplifier; Double Dynamic Switching Bias; Self-Cascode; Switched Capacitor

Full Text:

PDF

References


S. Yan and E. Sanchez-Sinencio, "Low voltage analog circuit design techniques: A tutorial," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 83, no. 2, pp. 179-196, 2000.

https://people.engr.tamu.edu/s-sanchez/607-lvtutorial-2000.pdf

H. Wakaumi, "A Switched-Capacitor Low-Pass Filter with Multiple-Channel Double-DSB OP Amplifiers," in 2021 International Conference on Electronics, Information, and Communication (ICEIC), 2021: IEEE, pp. 1-4.

https://doi.org/10.1109/ICEIC51217.2021.9369814

J.-T. Wu, Y.-H. Chang, and K. L. Chang, "1.2 V CMOS switched-capacitor circuits," in 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996: IEEE, pp. 388-389.

https://doi.org/10.1109/ISSCC.1996.488729

J.-f. Huang, J.-y. Wen, and Y.-j. Lin, "Chip design of a 10-MHz switched capacitor low-pass filter for wireless application," in 2014 Sixth International Conference on Wireless Communications and Signal Processing (WCSP), 2014: IEEE, pp. 1-5.

https://doi.org/10.1109/WCSP.2014.6992004

S. Rajput and S. S. Jamuar, "Low voltage analog circuit design techniques," IEEE Circuits and Systems Magazine, vol. 2, no. 1, pp. 24-42, 2002.

https://doi.org/10.1109/MCAS.2002.999703

B. Song, O. Kwon, I. Chang, H. Song, and K. Kwack, "A 1.8 V self-biased complementary folded cascode amplifier," in AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No. 99EX360), 1999: IEEE, pp. 63-65.

https://doi.org/10.1109/APASIC.1999.824030

D. Hisamoto et al., "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE transactions on electron devices, vol. 47, no. 12, pp. 2320-2325, 2000.

https://doi.org/10.1109/16.887014

N. Liao et al., "Low power adiabatic logic based on FinFETs," Science China Information Sciences, vol. 57, pp. 1-13, 02/01 2014, doi: 10.1007/s11432-013-4902-x.

https://doi.org/10.1007/s11432-013-4902-x

A. Kumar, B. Kaur, and M. Arora, "Evolution of Transistor Technology from BJT to FinFET–A study," in International Conference on Advanced Emerging Technology (ICAET), 2016.

https://research.ijcaonline.org/icaet2016/number3/icaet041.pdf

S. K. Saha, FinFET devices for VLSI circuits and systems. CRC Press, 2020.

https://doi.org/10.1201/9780429504839

S. Kundra, P. Soni, and A. Kundra, "Low power folded cascode OTA," International Journal of VLSI design & Communication Systems, vol. 3, no. 1, p. 127, 2012.

https://www.researchgate.net/publication/266886167_Low_Power_Folded_Cascode_OTA

B. Razavi, Design of analog CMOS integrated circuits. 2005.

https://books.google.com.tr/books/about/Design_of_Analog_CMOS_Integrated_Circuit.html?id=YXtqjwEACAAJ&redir_esc=y

T. Kulej and F. Khateb, "A 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS," IEEE Access, vol. 8, pp. 27459-27467, 2020.

https://doi.org/10.1109/ACCESS.2020.2972067

J. Kim, S. Song, and J. Roh, "A high slew-rate enhancement class-AB operational transconductance amplifier (OTA) for switched-capacitor (SC) applications," IEEE Access, vol. 8, pp. 226167-226175, 2020.

https://doi.org/10.1109/ACCESS.2020.3044608

M. Shirazi and A. Hassanzadeh, "Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models," AEU-International Journal of Electronics and Communications, vol. 82, pp. 136-144, 2017.

https://doi.org/10.1016/j.aeue.2017.08.013

A. Hassanzadeh and S. Hadidi, "Systematic approach for IG-FinFET amplifier design using gm/Id method," Analog Integrated Circuits and Signal Processing, vol. 109, no. 2, pp. 379-385, 2021/11/01 2021,

https://doi.org/10.1007/s10470-021-01917-9

R. A. Thakker et al., "A novel architecture for improving slew rate in FinFET-based op-amps and OTAs," Microelectronics Journal, vol. 42, no. 5, pp. 758-765, 2011.

https://doi.org/10.1016/j.mejo.2011.01.010

T. Tanzawa, "Innovation of switched-capacitor voltage multiplier: Part 2: Fundamentals of the charge pump," IEEE Solid-State Circuits Magazine, vol. 8, no. 2, pp. 83-92, 2016.

https://doi.org/10.1109/MSSC.2016.2543065

M. Karim and C. Brunette, "Switched Capacitor Circuits," 2023.

https://doi.org/10.1016/B978-0-12-819728-8.00061-9

B. J. Hosticka, R. W. Brodersen, and P. R. Gray, "MOS sampled data recursive filters using switched capacitor integrators," IEEE Journal of Solid-State Circuits, vol. 12, no. 6, pp. 600-608, 1977.

https://doi.org/10.1109/JSSC.1977.1050967

K. Martin, "Improved circuits for the realization of switched-capacitor filters," IEEE Transactions on Circuits and Systems, vol. 27, no. 4, pp. 237-244, 1980.

https://doi.org/10.1109/TCS.1980.1084808




DOI: https://doi.org/10.33180/InfMIDEM2025.105

Refbacks



Copyright (c) 2024 Firat KACAR

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.