Design and analysis of Low power Rapid Charge Holding Dynamic Latched Comparator

Jaspar vinitha sundari Thirunavukkarasu, Paramasivam K

Abstract


The need for high precision portable devices has raised the demand for better optimization of power and delay in various dynamic comparator topologies. In this paper, an efficient architecture that does timely yet rapid comparison with reduced power dissipation and optimal energy per comparison is proposed. Introducing an extra tail transistor in preamplifier of comparator, assists in holding the high gain for a time lapse. The latch is meanwhile ready with a minimum threshold value in its output nodes with the help of a pass transistor in between the output nodes. The conventional, hybrid, and proposed architecture, namely Low power rapid charge holding dynamic latched comparator (LRCHDLC) are simulated and verified for power, delay, and energy efficiency in cadence spectre 90 nm and 45 nm CMOS technology. The proposed technique shows a significant improvement in delay and power consumption when compared to conventional comparators. Monte Carlo simulation shows that the proposed technique is robust to the process mismatch, sustaining optimal power, delay and energy efficiency.

Keywords


Power, delay, Charge holding Latched comparator

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References

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DOI: https://doi.org/10.33180/InfMIDEM2025.401

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