0.18 µm CMOS power amplifier architecture comparison for a wideband Doherty configuration

Aleksandr Vasjanov, Vaidotas Barzdenas

Abstract


This paper presents a comparison between a classical and a self-biased two stage CMOS power amplifier (PA) suitable for a wideband Doherty (DPA) configuration. Both PAs are fully differential and have been implemented in IBM 7RF 0.18 µm CMOS process and are supplied from 1.8 V. Classical PA input impedance is shown to be matched from 1.6 GHz to 2.7 GHz @ S11 = -10 dB with external matching components. Self-biased PA his matched from 800 MHz to 1.75 GHz without any additional matching components and the bandwidth can be further increased to 2.15 GHz. Self-biased PA average PAE is 25.3 % which is 4.2 % higher than that of the classic PA. Both power amplifiers have an average output power of 10.5 dBm. The latter results show, that a self-biased PA architecture has more potential to be implemented in a wideband DPA configuration, compared to the classic PA arrangement. The active area for both on-chip PAs is 800 μm2, whereas the full IC chip size is 1.5 mm2. The dual PA ASIC has been designed to be enclosed in a 20-pin QFN package.

Keywords


CMOS, Power amplifier, Self-biased, Doherty, Wideband

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References


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