Radiation Induced Multiple Bit Upset Prediction and Correction in Memories using Cost Efficient CMC

Ahilan Appathurai, Deepa P

Abstract


This paper presents a cost efficient technique to correct Multiple Bit Upsets (MBUs) to protect memories against radiation. To protect memories from MBUs, many complex error correction codes (ECCs) were used previously, but the major issue is higher redundant memory overhead. The proposed method called counter matrix code (CMC) utilizes combinational ones counter and parity generator with less redundant memory overhead. CMC based on error predictor predicts the exact number of upsets before the actual error detection and correction process. The proposed technique uses Encode-Compare for minimizing the cost and increase the speed of the decoding process. The results are compared to the well-known codes such as CRC, Hamming and other matrix codes. The obtained results show that the correction coverage per cost (CCC) of the proposed scheme is higher than other traditional techniques. The MTTR of the proposed scheme is 3 times reduced than Xilinx CRC + Reload technique for 100% correction coverage. At the same time MTTR of the proposed scheme is 0.3ms, 0.2ms and 1.8ms less than I3D, DMC and MC, respectively with improved correction coverage.

Keywords


Multiple bit upsets (MBUs), memories, ones counter, parity codes, mean time to repair (MTTR).

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References


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