Radiation Induced Multiple Bit Upset Prediction and Correction in Memories using Cost Efficient CMC

Ahilan Appathurai, Deepa P


This paper presents a cost efficient technique to correct Multiple Bit Upsets (MBUs) to protect memories against radiation. To protect memories from MBUs, many complex error correction codes (ECCs) were used previously, but the major issue is higher redundant memory overhead. The proposed method called counter matrix code (CMC) utilizes combinational ones counter and parity generator with less redundant memory overhead. CMC based on error predictor predicts the exact number of upsets before the actual error detection and correction process. The proposed technique uses Encode-Compare for minimizing the cost and increase the speed of the decoding process. The results are compared to the well-known codes such as CRC, Hamming and other matrix codes. The obtained results show that the correction coverage per cost (CCC) of the proposed scheme is higher than other traditional techniques. The MTTR of the proposed scheme is 3 times reduced than Xilinx CRC + Reload technique for 100% correction coverage. At the same time MTTR of the proposed scheme is 0.3ms, 0.2ms and 1.8ms less than I3D, DMC and MC, respectively with improved correction coverage.


Multiple bit upsets (MBUs), memories, ones counter, parity codes, mean time to repair (MTTR).

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C. Argyrides, C. Lisboa, L. Carro and D.K. Pradhan, “ A soft error robust and power aware memory design ” in Proc. 20th Annu, Symp, Integr, Circuits Syst Des (SBCCI), Sep.2007, pp.300–305. www.inf.ufrgs.br/~calisboa/.../SlidesSBCCI2007ETLPRAM.pdf

M.J. Wirthlin, “FPGAs Operating In A Radiation Environment: Lessons Learned From FPGA In Space,” workshop on electronics for particle physics, Oxford, U.K , September 2012, pp. 17–21. https://indico.cern.ch/event/.../twepp_wirthlin_Sept_2012.ppt.pdf

Xilinx, “Device Reliability Report, UG116, v10.1”, August. 2014. juhuj.com/open-file-pdf-convert-pdf-download-ug116.htm

D. Radaelli, H. Puchner, S. Wong, and S. Daniel, “Investigation of multi-bit upsets in a 150 nm technology SRAM device,” IEEE Trans.Nucl. Sci., vol. 52, no. 6, pp. 2433–2437, Dec. 2005. ieeexplore.ieee.org/document/1589220/

R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Rel., vol. 5, no.3, pp. 305–316, Sep. 2005. ieeexplore.ieee.org/document/1545891/

ITRS 2002. [Online]. Available: http://public.itrs.net

P. M. B. Rao, M. Ebrahimi, R. Seyyedi, and M. B. Tahoori, “Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes,” in Proc. 51st ACM/EDAC/IEEE Design Autom. Conf. (DAC), Jun. 2014, pp. 1–6. http://ieeexplore.ieee.org/document/6881539/?reload=true&arnumber=6881539

A. Sanchez-Macian, P. Reviriego, J.A. Maestro, “Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes Through Selective Shortening and Bit Placement,” IEEE Trans. Device Mater. Rel. ,vol.14,no.1,pp.574-576,March2014. http://ieeexplore.ieee.org/document/6217302/

D. Houghton, “The Engineer’s Error Coding Handbook”. Chapman and Hall, London, U.K , 1997. www.springer.com/gp/book/9780412790706

P. Reviriego, M. Flanagan, and J. A. Maestro, “A (64,45) triple error correction code for memory applications,” IEEE Trans. Device Mater. Rel., vol. 12, no. 1, pp. 101–106, Mar. 2012. ieeexplore.ieee.org/document/6026914/

C. Argyrides, D. K. Pradhan, and T. Kocak, “Matrix codes for reliable and cost efficient memory chips,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 3, pp. 420–428, Mar. 2011. ieeexplore.ieee.org/document/5352255/

Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao, "Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.22, no.1, pp.127-135, Jan. 2014. http://ieeexplore.ieee.org/document/6487418/

R. Naseer and J. Draper, “Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs,” in Proc. 34th Eur. Solid-State Circuits, Sep. 2008, pp. 222–225. www.isi.edu/~draper/papers/esscirc08.pdf

A. Ahilan, P. Deepa, “Design for Built-In FPGA Reliability via Fine-Grained 2-D Error Correction Codes”, Microelectronics Reliability, vol. 55, pp. 2108-2112, Aug. –Sep. 2015. http://www.sciencedirect.com/science/article/pii/S0026271415001675?np=y

G. Neuberger, D. L. Kastensmidt, and R. Reis, “An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories,” IEEE Design Test Comput., vol. 22, no. 1, pp. 50–58, Jan.–Feb. 2005. https://www.lume.ufrgs.br/bitstream/handle/10183/27598/000459042.pdf?sequence=1

S. Liu, P. Reviriego, and J. A. Maestro, “Efficient majority logic fault detection with difference-set codes for memory applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 148–156, Jan. 2012. http://iosrjournals.org/iosr-jece/papers/Vol8-Issue2/M0827178.pdf

Appathurai, A.; Deepa, P., "Design for reliablity: A novel counter matrix code for FPGA based quality applications," in Proc. 6th Asia Symposium on Quality Electronic Design (ASQED), Aug. 2015, pp.56-61. http://ieeexplore.ieee.org/document/7274007/

L. Jones, “Single event upset (SEU) detection and correction using Virtex-4 devices,” Xilinx Corporation, San Jose, CA, USA, Appl. Note XAPP714, 2007. http://www.eng.auburn.edu/~strouce/class/bist/CATA09seu.pdf

Xilinx, “LogiCORE IP soft error mitigation controller, PG036, v3.4” San Jose, CA, USA, 2012. www.xilinx.com/support/documentation/ip.../v3_4/pg036_sem.pdf

E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, “Impact of scaling on neutron induced soft error in SRAMs from an 250 nm to a 22 nm design rule,” IEEE Trans. Electron Devices, vol. 57, no. 7,

pp. 1527–1538, Jul. 2010. http://ieeexplore.ieee.org/document/5467170/

E. Costenaro, D. Alexandrescu, K. Belhaddad, and M. Nicolaidis, “A practical approach to single event transient analysis for highly complex design,” J. Electron. Test., vol. 29, no. 3, pp. 301–315, 2013. http://ieeexplore.ieee.org/document/6104439/

M. Ebrahimi, P.M.B. Rao,; R. Seyyedi,; M.B . Tahoori, "Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 148–156, Jan. 2012. http://ieeexplore.ieee.org/document/7104165/

JEDEC89C Standard, [Online]. Available: http://www.jedec.org/standards-documents, accessed Apr. 2015.


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