Synthesizable 2D Vernier TDC based on gated ring oscillators

Marijan Jurgo, Romualdas Navickas

Abstract


Time to digital converter (TDC) is a device, which measures time interval between two edges of signals and converts it to digital code. Lately it is used as phase detector in all-digital frequency synthesizers. One of main parameters of TDC is resolution, which describes smallest time interval, which can be measured using TDC. Resolution of basic inverter-based TDC improves with reduction of delay of inverter in modern nanometric CMOS technology nodes. But in more mature technologies delay of inverter does not provide needed TDC resolution. In this paper sub-inverter-resolution 2D Vernier TDC, which is based on gated ring oscillators and is implemented in VHDL hardware description language for easy migration to various technology nodes, is presented. It is synthesized, placed and routed in 65 nm CMOS technology. Main blocks of TDC are two gated ring oscillators, their lap and edge counters, arbiter matrix, output decoder and control block. Frequency and single stage delay of gated ring oscillators is changed by switching parallel-connected sections of three-stage oscillators. Tuning step of single stage delay of gated ring oscillator, which is equal to resolution of TDC, can be changed from 3.2 to 0.8 ps at typical operation conditions, when number of enabled stages of oscillator is changed from 22 to 48. TDC occupies 123,0 µm × 148,8 µm area of silicon.Time to digital converter (TDC) is a device, which measures time interval between two edges of signals and converts it to digital code. Lately it is used as phase detector in all-digital frequency synthesizers. One of main parameters of TDC is resolution, which describes smallest time interval, which can be measured using TDC. Resolution of basic inverter-based TDC improves with reduction of delay of inverter in modern nanometric CMOS technology nodes. But in more mature technologies delay of inverter does not provide needed TDC resolution. In this paper sub-inverter-resolution 2D Vernier TDC, which is based on gated ring oscillators and is implemented in VHDL hardware description language for easy migration to various technology nodes, is presented. It is synthesized, placed and routed in 65 nm CMOS technology. Main blocks of TDC are two gated ring oscillators, their lap and edge counters, arbiter matrix, output decoder and control block. Frequency and single stage delay of gated ring oscillators is changed by switching parallel-connected sections of three-stage oscillators. Tuning step of single stage delay of gated ring oscillator, which is equal to resolution of TDC, can be changed from 3.2 to 0.8 ps at typical operation conditions, when number of enabled stages of oscillator is changed from 22 to 48. TDC occupies 123,0 µm × 148,8 µm area of silicon.

Keywords


CMOS, integrated circuit, time to digital converter, Vernier, gated ring oscillator

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References


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