A New Low-Power CMOS Sample-and-Hold Circuit Based on High-Speed Dynamic Body Biased Switches

Mohammad Hasan-Sagha, Mohsen Jalali

Abstract


In this paper, a low-power open-loop CMOS sample-and-hold (S/H) circuit with improved linearity is presented. The incorporated switches utilize dynamic body connection technique to reduce distortions due to threshold voltage variations during track mode as well as signal feedthrough in the hold mode. To accomplish dual-edge sampling characteristic and differential operation, the proposed S/H circuit utilizes two pairs of the proposed switch and a 2:1 multiplexer. A current mode logic multiplexer without tail current is utilized to reduce power consumption while still fulfilling the speed and linearity requirements. The proposed S/H circuit is designed in a 90-nm CMOS process where it consumes approximately 610 μW from a 1.2 V supply voltage. A SFDR of about 73 dB is achieved when sampling a 1 GHz differential sinusoidal input at 2 GS/s rate using both edges of a 1 GHz clock signal.

Keywords


Sample and hold circuits; high-speed switches; body biasing; dual-edge sampling.

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References


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