Design of Fault-Tolerant Reversible Floating Point Division

Kamaraj A, Marichamy P

Abstract


Nowadays, power dissipation and the size of the computational devices are playing a major role in semiconductor industry. The size of a transistor limits the scaling of the semiconductor devices. In turn, an alternative technology is a reversible logic based computational devices. In this paper, new reversible KMD gates capable of producing many logical functions are proposed. The proposed gates satisfy the fundamental properties of reversible logic, reversibility & universality. The functionality of the gates is verified in Quantum Cellular Automata (QCA), which is popular for validating reversible logic. In addition, the proposed gates are fault-tolerant as it is having parity preservation. An N-bit fault-tolerant reversible floating point division unit (FTRFPD) is designed to the IEEE 754 single precision standard using the above fault-tolerant reversible gates. It has parallel adder, latch, multiplexer, shift register, rounding and normalization register. All the functional blocks are fault-tolerant in nature since they are constructed from the FT Gates. The FTRFPD is capable of dividing two numbers using the procedural algorithm. The QCA based simulation results confirm that the designed unit is having improved Quantum Cost of 9.85%, 29.63% of Delay and 33.54 % Number of Gates over the existing designs.


Keywords


Reversible Logic; Quantum Cost; Delay; Garbage Outputs

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