Design and Performance Analysis of SELBOX Junctionless FinFET

Rajeev Pankaj Nelapati, Sivasankaran K

Abstract


In this work, we analyzed the performance of a selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure are studied and compared with the conventional and hybrid ( or inverted-T ) JLFinFETs. The ION of the proposed structure is 1.43x times better than the ION of the SOI-JLFinFET because of added advantage of different technologies such as 2D- ultra-thin-body (UTB), 3D-FinFET and SELBOX. The proposed device was modeled using sprocess and simulation study was carried using sdevice.  Various analog parameters such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg) and intrinsic gain (A0) are evaluated for the proposed device. The proposed structure with a minimum feature size of 10nm  exhibits better TGF, fT, VEA, and A0 in the deep-inversion region of operation.

Keywords


Junctionless FinFET; SELBOX-JLFinFET; Self heating; fT; TGF;

Full Text:

PDF

References


Saremi, Mehdi, Behzad Ebrahimi, Ali Afzali Kusha, and Mohammad Saremi. "Process variation study of ground plane SOI MOSFET." In Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on, pp. 66-69. IEEE, 2010.

Saremi, Mehdi, Masoumeh Saremi, Hamid Niazi, Maryam Saremi, and Arash Yazdanpanah Goharrizi. "SOI LDMOSFET with Up and Down Extended Stepped Drift Region." Journal of Electronic Materials 46, no. 10 (2017): 5570-5576.

Li, Yiming, Hung-Mu Chou, and Jam-Wem Lee. "Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs." IEEE Transactions on Nanotechnology 4, no. 5 (2005): 510-516.

Hisamoto, Digh, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Charles Kuo, Erik Anderson, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu. "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm." IEEE Transactions on Electron Devices 47, no. 12 (2000): 2320-2325.

Zhang, Weimin, Jerry G. Fossum, and Leo Mathew. "The ITFET: A novel FinFET-based hybrid device." IEEE Transactions on Electron Devices 53, no. 9 (2006): 2335-2343.

Fahad, Hossain M., Chenming Hu, and Muhammad M. Hussain. "Simulation study of a 3-D device integrating FinFET and UTBFET." IEEE Transactions on Electron Devices 62, no. 1 (2015): 83-87.

Pradhan, K. P., and P. K. Sahu. "Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high-performance application." Superlattices and Microstructures 90 (2016): 191-197.

Pradhan, K. P., M. G. C. Andrade, and P. K. Sahu. "Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs." Superlattices and Microstructures 100 (2016): 335-341.

Pradhan, K. P., and P. K. Sahu. "Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs." Materials Science in Semiconductor Processing 57 (2017): 185-189.

Pradhan, K. P., and P. K. Sahu. "Investigation of asymmetric high-k underlap spacer (AHUS) hybrid FinFET from temperature perspective." Microsystem Technologies 23, no. 7 (2017): 2921-2926.

Nelapati, Rajeev Pankaj, and K. Sivasankaran. "Impact of self-heating effect on the performance of hybrid FinFET." Microelectronics Journal 76 (2018): 63-68.

Colinge, Jean-Pierre, Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, Pedram Razavi et al. "Nanowire transistors without junctions." Nature nanotechnology 5, no. 3 (2010): 225.

Han, Ming-Hung, Chun-Yen Chang, Hung-Bin Chen, Jia-Jiun Wu, Ya-Chi Cheng, and Yung-Chun Wu. "Performance comparison between bulk and SOI junctionless transistors." IEEE Electron Device Letters 34, no. 2 (2013): 169-171.

Zhang, Zheng Xuan, Qing Lin, Ming Zhu, and Cheng Lu Lin. "A new structure of SOI MOSFET for reducing self-heating effect." Ceramics international 30, no. 7 (2004): 1289-1293.

Raleva, K., D. Vasileska, A. Hossain, S-K. Yoo, and S. M. Goodnick. "Study of self-heating effects in SOI and conventional MOSFETs with electro-thermal particle-based device simulator." Journal of Computational Electronics 11, no. 1 (2012): 106-117.

Narayanan, M. R., Hasan Al-Nashash, Baquer Mazhari, and Dipankar Pal. "Studies and minimization of kink effect in SOI MOSFET devices with SELBOX structure." In Microelectronics, 2008. ICM 2008. International Conference on, pp. 232-235. IEEE, 2008.

Khan, Uzma, Bahniman Ghosh, Md Waseem Akram, and Akshaykumar Salimath. "A comparative study of SELBOX-JLT and SOI-JLT." Applied Physics A 117, no. 4 (2014): 2281-2288.

Guide, Sentaurus Process User, and G. Version. "Synopsys." Inc., Jun (2012).

Gundapaneni, Suresh, Swaroop Ganguly, and Anil Kottantharayil. "Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling." IEEE Electron Device Letters 32, no. 3 (2011): 261-263.

Guide, Sentaurus Device User, and G. Version. "Synopsys." Inc., Jun (2012).

Silveira, Flandre, Denis Flandre, and P. G. A. Jespers. " gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA." IEEE Journal of Solid-State Circuits 31, no. 9 (1996): 1314-1319.




DOI: https://doi.org/10.33180/InfMIDEM2019.104

Refbacks

  • There are currently no refbacks.