Design and Performance Analysis of SELBOX Junctionless FinFET

Rajeev Pankaj Nelapati, Sivasankaran K


In this work, we analyzed the performance of a selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure are studied and compared with the conventional and hybrid ( or inverted-T ) JLFinFETs. The ION of the proposed structure is 1.43x times better than the ION of the SOI-JLFinFET because of added advantage of different technologies such as 2D- ultra-thin-body (UTB), 3D-FinFET and SELBOX. The proposed device was modeled using sprocess and simulation study was carried using sdevice.  Various analog parameters such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg) and intrinsic gain (A0) are evaluated for the proposed device. The proposed structure with a minimum feature size of 10nm  exhibits better TGF, fT, VEA, and A0 in the deep-inversion region of operation.


Junctionless FinFET; SELBOX-JLFinFET; Self heating; fT; TGF;

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