FPGA implementation of time-area-efficient Elliptic Curve Cryptography for entity authentication

Kamaraj Arunachalam, Marichamy Perumalsamy


In the ever increasing wireless reliant technologies, communications and devices, the demand for effective security with low hardware and high speed is wanting in the cryptography domain. Among the various cryptographic algorithms, the Elliptic Curve Cryptography (ECC) provides an attractive solution for this demand. In this paper, the Remote Keyless system Authentication process using the ECC has been implemented in Field Programmable Gate Array (FPGA). The designed ECC processor supports 256-bit point multiplication and point addition on the Koblitz curve secp256k1. The scalar multiplication has been performed with the faster multiplier Urdhva Tiryagbhyam. Additionally, pipelining has been incorporated in order to speed up the multiplication process of the processor. The proposed ECC processor performs single point multiplication of 256-bit in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, reduces time consumption by 22.36%, which in turn increases the throughput by 22.36%. The proposed pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, operating frequency, area-delay product and throughput. Hence, the implementation of the proposed method offers time-area-efficient fast scalar multiplication with effective hardware utilization without any compromise in security level. 


Urdhva Tiryagbhyam; Pipeline; Remote Keyless system Authentication; FPGA

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DOI: https://doi.org/10.33180/InfMIDEM2022.203


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