Design, Fabrication and Measurement of LDNMOS-SCR Devices with Appropriate ESD Pro-tection Window for 18V HV CDMOS Process

Su Xue Bing, Wang Yang, Jin Xiang Liang, Yang Hong Jiao, Zhou Zi Jie


LDMOS embedded SCR is a normal way to improve the ESD robustness for smart power technologies, but it doesn’t always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been inves-tigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. TLP testing results demonstrated that those devices successfully elevate the second breakdown current It2 from original 1.146A to above 3A; source isolated device has a lower Vt1 (45.79V) than source non-isolated devices; the Vh of the four devices is related to their structure, and their Ih are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low Vt1, small Ron and sufficiently big Ih.


ESD window; LDMOS embedded SCR; TCAD device simulation; TLP

Full Text:



R. K. Williams, M. N. Darwish, R. A. Blanchard, R. Siemieniec, P. Rutter and Y. Kawaguchi, "The Trench Power MOSFET—Part II: Application Specific VDMOS, LDMOS, Packaging, and Reliability," IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 692-712, March 2017, https://doi.10.1109/TED.2017.2655149.

J. S. Meiguni et al., "Transient Analysis of ESD Protection Circuits for High-Speed ICs," IEEE Transactions on Electromagnetic Compatibility, vol. 63, no. 5, pp. 1312-1321, Oct. 2021, https://doi. 10.1109/TEMC.2021.3071644.

Y. J. Chen, S. L. Chen and M. H. Lee et al., "ESD-reliability influence on LV/HV MOSFET devices by different zapping-voltage steps in the transmission-line pulse testing," in 2017 International Conference on Applied System Innovation (ICASI), 2017, pp. 1407-1410, https://doi.10.1109/ICASI.2017.7988171.

C. Dai and M. Ker, " Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology. Electron Devices," IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3519-3523, Aug. 2017, https://doi. 10.1109/TED.2017.2717970.

Liang, H. , Si, X. , and Cao, H. , et al., " Investigation on LDMOS-SCR with high holding current for high voltage ESD protection," Microelectronics Reliability, vol. 61, no.JUN., pp. 120-124, Jun.2016,

N. K. Kranthi, B. S. Kumar, A. Salman, G. Boselli and M. Shrivastava, "Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip," in 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2019, pp. 407-410, https://doi.10.1109/ISPSD.2019.8757641.

Wang, Y.,Jin, X. L.,Zhou A. C, "Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology," J. Cent. South Univ. vol. 22, pp. 552-559, 2015, https://doi. 10.1007/s11771-015-2555-1

Liu, Z. , Song, W. Q. , and Du, F. , et al., "Improved LDMOS-SCR for high-voltage electrostatic discharge (ESD) protection applica-tions," Electronics Letters, Vol. 56, No. 13, pp. 680-682,Jun.2020,

W. Chang and M. Ker, "The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology," IEEE Transactions on Device and Materials Reliability, vol. 7, no. 2, pp. 324-332, June 2007, https://doi.10.1109/TDMR.2007.901185.

M. Ker, C. Hsu and W. Chen, "ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup," in Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 989-992,https://doi: 10.1109/ISCAS.2010.5537378.

Jian-Hsing Lee et al., "Novel ESD protection structure with embedded SCR LDMOS for smart power technology," in 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002, pp. 156-161, https://doi.10.1109/RELPHY.2002.996629.

D. Jing and C. Xingbi, "A novel SCR-LDMOS for high voltage ESD protection," 2015 IEEE 11th International Conference on ASIC (ASICON), 2015, pp. 1-4, https://doi.10.1109/ASICON.2015.7517155.

Liang, Hailian , et al, "A modified LDMOS device with improved ESD protection performance, " Ieej Transactions on Electrical & Electronic Engineering, vol. 9, no. 6, pp. 700-702, Sep. 2014,

Liang, H. , Cao, H. , et al, "Design and optimization of LDMOS-SCR devices with improved ESD protection performance," Microelectronics and reliability, vol. 61, pp. 115-117, Jun.2016,

Chen, Z. , Lu, W. , Wu, M. , et al, "A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability, " Solid-State Elec-tronics, vol. 161, pp. 107640, Nov. 2016,

Liu, Z. , Song, Hou, F. , et al, "Improved LDMOS-SCR for high-voltage electro-static discharge (ESD) protection applications," Electronics Letters, vol. 56, no. 13, pp. 680-682, Jun. 2020,

Xiao, J. , Qiao, M. , Zhao, Q. I. , Liang, L. , et al, "A High Holding Current SCR (HHI-SCR) for High Voltage ESD Protection," Electronics & Packaging, vol. 19, no. 5, pp. 45-47, May. 2019, https://doi.10.16257/j.cnki.1681-1070.2019.0057.

Shen, H. Y. , Dong, S. R. , Ze-Kun, X. U. , and Tao, H. U. , et al, "Improved LDMOS for ESD Protection of High Voltage BCD Process, " in 2019 IEEE 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) IEEE, 2019,https://doi.10.1109/IPFA47161.2019.8984830.

Wang, T. , Huang, L. , Pan, J. , et al, "Analysis of ESD Protection Characteristics and Optimization for LDMOS Devices, "Electronics & Packaging, vol. 17, no. 8, pp. 41-43,https://doi.10.16257/j.cnki.1681-1070.2017.0102.



  • There are currently no refbacks.

Copyright (c) 2022 Su Xue Bing, Wang Yang, Jin Xiang Liang, Yang Hong Jiao, Zhou Zi Jie

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.