Free software support for compact modelling with Verilog-A

Árpád Bűrmen, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver, Sašo Tomažič

Abstract


Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and  free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.


Keywords


hardware description language; verilog-a; analog circuits; circuti simulation; compact models

Full Text:

PDF

References


Flake, P., et.al. Verilog HDL and its ancestors and descendants. Proceedings of the ACM on Programming Languages, vol. 4 (2020), pp. 1–90.

1364-1995 - IEEE Standard Verilog Hardware Description Language, 1996, doi:10.1109/IEEESTD.1996.81542.

1364-2001 - IEEE Standard Verilog Hardware Description Language, 2001, doi:10.1109/IEEESTD.2001.93352.

1364-2005 - IEEE Standard for Verilog Hardware Description Language,

, doi:10.1109/IEEESTD.2006.99495.

1800-2005 - IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language, 2005, doi:10.1109/IEEESTD.2005.97972.

1800-2009 - IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language, 2009, doi:10.1109/IEEESTD.2009.5354441.

1800-2012 - IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language, 2013, doi:10.1109/IEEESTD.2013.6469140.

1800-2017 - IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language, 2018, doi:10.1109/IEEESTD.2018.8299595.

1800-2023 - IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language, 2024, doi:10.1109/IEEESTD.2024.10458102.

Verilog-A Language Reference Manual, Analog Extensions to Verilog HDL, https://www.siue.edu/∼gengel/ece585WebStuff/OVI VerilogA.pdf, 2024.

Verilog-AMS Language Reference Manual, version 2.4.0, [online] Available: https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf

Verilog-AMS standard, [online] Available: https://www.accellera.org/downloads/standards/v-ams

Saber(R) MAST Language User Guide, Synopsys, 2008.

SystemVerilog AMS (Analog/Mixed-Signal) Working Group, [online] Available: https://www.eda.org/activities/working-groups/systemverilog-ams

Ho, C.-W., Ruehli, A., and Brennan, P., The Modified Nodal Approach

to Network Analysis. Proc. 1974 Int. Symposium on Circuits and Systems,

San Francisco. pp. 505–509.

BSIM Group, [online] Available: http://bsim.berkeley.edu/

VA-BSIM48, [online] Available: https://github.com/cogenda/VA-BSIM48

Compact Model Coalition, [online] Available: https://si2.org/cmc/

Weil, P., McNamee, L., Simulation of excess phase in bipolar transistors. IEEE Trans. Circuits Syst., vol. 25 (1978), pp. 114-116.

Ward, D. E., Dutton, R. W., A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits, vol. 13 (1978), pp. 703-708.

Yang, P., Epler, B. D., Chatterjee, P. K., An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation, IEEE J. Solid-State Circuits, vol. 18 (1983), pp. 128-138.

Spectre Circuit Simulator Reference, Cadence, 2003.

Steer, M. B., Kriplani, N. M., Luniya, S., Hart, F., Lowry, J., Christoffersen, C. E., fREEDA: An Open Source Circuit Simulator, 2006 International Workshop on Integrated Nonlinear Microwave and Millimeter-Wave Circuits, IEEE, January 2006.

Lemaitre, L., McAndrew, C., Hamm, S., ADMS-automatic device model synthesizer, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, IEEE, May 2002.

HSPICE MOSFET Models Manual, Synopsys, 2005.

Extensible Markup Language (XML), [online] Available: http://www.w3.org/XML.

Glib-2.0, [online] Available: https://docs.gtk.org/glib/

XSL transformations (XSLT), [online] Available: http://www.w3.orglTR/xslt

Ngspice - open source spice simulator, [online] Available: https://ngspice.sourceforge.io/

Gnu Circuit Analysis Package - Git Repositories, [online] Available: https://savannah.gnu.org/git/?group=gnucap

Circuit simulator of the Qucs project, [online] Available: https://github.com/Qucs/qucsator

Xyce - Parallel electronic simulation, [online] Available: https://xyce.sandia.gov/

Xyce/ADMS Users Guide, [online] Available: https://xyce.sandia.gov/documentation-tutorials/xyce-adms-users-guide/

Ngspice user’s manual (version 38), [online] Available: https://ngspice.sourceforge.io/docs/ngspice-38-manual.pdf

Kuthe, P., Müller, M., Krattenmacher, M., Schröter, M., OpenVAF Verilog-A Compiler, MOSAK Feb.25 2022, February 2022.

VerilogAE: An Open Source Verilog-A Compiler for Compact Model Pa-

rameter Extraction, Journal of Electron Devices Society, vol. 8 (2020), pp.

-1423.

OpenVAF - Performance, [online] Available: https://openvaf.semimod.de/docs/details/performance/

Bűrmen, A., VACASK - Verilog-A Circuit Analysis Kernel, [online] Available: https://codeberg.org/arpadbuermen/VACASK

Modelgen-Verilog GIT repository [online] Available: https://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git

Open Source Device Interface (OSDI) Specification -Working Draft, SemiMod, 2022, [online] Available: https://openvaf.semimod.de/osdi/osdi v0p3.pdf

The LLVM Compiler Infrastructure, [online] Available: https://llvm.org/

Puhan, J, Bűrmen, Á., Fajfar, I., Tuma, T., Spice Opus [online] Available: http://www.spiceopus.si/

Salfelder, F., Verilog-AMS in Gnucap, Free Silicon Conference (FSiC) 2023 [online] Available: http://felix.salfelder.org/gnucap/fsic gnucap23.pdf

The Trilinos Project Website, [online] Available: https://trilinos.github.io

Verley, J., Keiter, E., Xyce/ADMS and the Xyce Verilog-A Path Forward, Q1 2022 MOS-AK Panel, [online] Available: https://mos-ak.org/panel Q1 2022/presentations/Verley Xyce MOS-AK Q1 2022.pdf

Chandra, R., et.al., Parallel Programming in OpenMP, Morgan Kaufmann,

Sanders, J., Kandrot, E., CUDA by Example: An Introduction to General-Purpose GPU Programming, Addison-Wesley Professional, 2010.

Kundert., K., SPARSE 1.3, [online] Available:https://www.netlib.org/sparse/

Davis, T. A., Natarajan, E. P., Algorithm 907: KLU, a direct sparse solver for circuit simulation problems. ACM Trans. Math. Softw., vol. 37 (2010), pp. 1-17.


Refbacks

  • There are currently no refbacks.


Copyright (c) 2024 Árpád Bűrmen, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver, Sašo Tomažič

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.