Design of a Low-Power Phase-Frequency Detector and Gain-Boosting Charge Pump for GHz-Range Applications in 180-nm CMOS Technology

Hamid Gholipour Golroudbari, Hadi Dehbovid, Reza Yousefi, Seyed Saleh Ghoreishi Amiri, Habib Adarang

Abstract


Phase-Frequency Detector (PFD) and Charge Pump (CP) are crucial components in Phase-Locked Loops (PLL) and Delay-Locked Loops (DLL), significantly impacting synchronization accuracy and system stability. In this paper, a new PFD based on dynamic logic with a minimal number of devices is designed, providing low delay and proper logic output levels. Additionally, a novel CP employing the gain-boosting technique and utilizing a cascode amplifier is proposed, achieving higher DC-gain and better current matching. The proposed design aims to minimize power consumption to the microwatt level, reduce circuit area, and achieve an operating frequency up to 3 GHz. Simulation results in 180-nm CMOS technology using Cadence software demonstrate that the proposed circuit offers lower power consumption, smaller area, and improved dynamic performance compared to conventional designs, making it well-suited for PLL and DLL applications in high-frequency communication systems.

Keywords


Phase-Frequency Detector (PFD), Charge Pump (CP), Gain Boosting, Low Power, Current Matching

Full Text:

PDF

References


N. Kumar and M. Kumar, "Design of low power and high speed phase detector," in 2016 2nd International Conference on Contemporary Computing and Informatics (IC3I), 2016, pp. 82–86, doi: 10.1109/ic3i.2016.7918048.

Naveed and J. Dix, "Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI," Journal of Low Power Electronics and Applications, vol. 13, no. 4, p. 64, 2023, doi: 10.3390/jlpea13040064.

H.-H. Chen, Z.-H. Wong, and S.-L. Chen, "Design of delay-locked loop for wide frequency locking range," in 2013 Interna-tional SoC Design Conference (ISOCC), 2013, pp. 175–178, doi: 10.1109/isocc.2013.6864033.

H. S. Raghav, S. Maheshwari, M. Srinivasarao, and B. P. Singh, "Design of low power, low jitter DLL tested at all five corners to avoid false locking," in 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012, pp. 312–315, doi: 10.1109/smelec.2012.6417201.

K.-C. Kuo, C.-Y. Chang, and S.-H. Li, "Low power delay locked loop with all digital controlled SAR delay cell," in 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012, pp. 160–163, doi: 10.1109/apccas.2012.6418986.

P. Kaul, H. Gao, X. He, and P. Baltus, "An UWB, Low-Noise, Low-Power Quadrature VCO using Delay-Locked Loop in 40-nm CMOS for Image-Rejection Receivers," in 2018 IEEE Inter-national Symposium on Circuits and Systems (ISCAS), 2018, pp. 1–4, doi: 10.1109/iscas.2018.8350984.

J.-S. Wang, C.-Y. Cheng, P.-Y. Chou, and T.-Y. Yang, "A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture," IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2635–2644, Nov. 2015, doi: 10.1109/jssc.2015.2466443.

T. I. Badal, P. Maroofee, M. A. Sobhan Bhuiyan, L. F. Rah-man, M. Bin Ibne Reaz, and M. A. Mukit, "Low power delay locked-loop using 0.13μm CMOS technology," in 2016 Interna-tional Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), 2016, pp. 245–248, doi: 10.1109/icaees.2016.7888033.

S. K. Garg and B. Singh, "A novel design of an efficient Low Power Phase Frequency Detector for Delay Locked Loop," in 2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), 2016, pp. 298–302, doi: 10.1109/icpeices.2016.7853318.

V. Kumar and M. Khosla, "Design of a low power Delay Locked Loop based Clock and Data Recovery circuit," in 2011 Annual IEEE India Conference (INDICON), 2011, pp. 1–4, doi: 10.1109/indcon.2011.6139507.

M. E. Quchani and M. Maymandi-Nejad, “Design of a Low-Power Linear SAR-Based All-Digital Delay-Locked Loop,” 2019 27th Iranian Conference on Electrical Engineering (ICEE). IEEE, pp. 118–124, Apr. 2019. doi: 10.1109/iraniancee.2019.8786365.

S. Kim, S. Oh, K. Kang, and K.-Y. Lee, “A 8.9 mW, 0.6–2 GHz fast locking delay-locked loop using dual delay lines with phase blender,” 2018 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, pp. 1–3, Jan. 2018. doi: 10.23919/elinfocom.2018.8330582.

L. W. Loon, M. B. I. Reaz, M. A. S. Bhuiyan, Mohd. Marufuzzaman, and Md. T. I. Badal, “A study on low power phase frequency detectors for delay locked loop,” 2016 Inter-national Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES). IEEE, pp. 147–150, Nov. 2016. doi: 10.1109/icaees.2016.7888027.

B. P. Dorta-Naranjo, V. Araña-Pulido, F. Cabrera-Almeida, and E. J. Yguácel, “A 2–18-GHz 360° Phase Detector Based on Switched Dual Multipliers and Fixed Delay Lines,” IEEE Transactions on Instrumentation and Measurement, vol. 74. Institute of Electrical and Electronics Engineers (IEEE), pp. 1–10, 2025. doi: 10.1109/tim.2024.3522336.

V. A. Pulido, F. Cabrera-Almeida, P. Quintana-Morales, and E. Mendieta-Otero, “Novel Phase Detector Measurement Procedure Using Quasi-Synchronized RF Generator,” IEEE Transactions on Instrumentation and Measurement, vol. 72. Institute of Electrical and Electronics Engineers (IEEE), pp. 1–9, 2023. doi: 10.1109/tim.2023.3330210.

Y. Liang, C. C. Boon, C. Li, and Q. Chen, “A 28.8-to-43.2 GHz 79.8 fsrms Jitter and −78.5 dBc Reference Spur PLL Ex-ploiting Complementary Mixing Phase Detector With Mis-match Calibration,” IEEE Transactions on Microwave Theory and Techniques, vol. 72, no. 5. Institute of Electrical and Elec-tronics Engineers (IEEE), pp. 2716–2733, May 2024. doi: 10.1109/tmtt.2024.3363465.

J. Yang, Q. Pan, J. Yin, and P.-I. Mak, “A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 71, no. 8. Institute of Electrical and Electronics Engineers (IEEE), pp. 3596–3604, Aug. 2023. doi: 10.1109/tmtt.2023.3242333.

F. E. Saraji, A. Ghorbani, and S. M. Anisheh, "Design of a delay locked loop with low power and high operating frequen-cy range characteristics in 180-nm CMOS process," Analog Integrated Circuits and Signal Processing, vol. 118, no. 1, pp. 121–131, 2023, doi: 10.1007/s10470-023-02203-6.

L. Wang, L. Liu, and H. Chen, "An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 6, pp. 421–425, Jun. 2010, doi: 10.1109/tcsii.2010.2048379.

Y.-G. Chen, H.-W. Tsao, and C.-S. Hwang, "A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 2, pp. 270–280, Feb. 2013, doi: 10.1109/tvlsi.2011.2182216.

R.-J. Yang and S.-I. Liu, "A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algo-rithm," IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 361–373, Feb. 2007, doi: 10.1109/jssc.2006.889381.

E. Bayram, A. F. Aref, M. Saeed, and R. Negra, "1.5–3.3 GHz, 0.0077 mm², 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in 0.13 μm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 39–50, Jan. 2018, doi: 10.1109/tcsi.2017.2715899.

J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Nov. 1996, doi: 10.1109/jssc.1996.542317.

A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuit, New York: IEEE Press, 2001.

H. Dehbovid, H. Adarang, and M. B. Tavakoli, "Nonlinear analysis of VCO jitter generation using Volterra series," COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 37, no. 2, pp. 755–771, 2018, doi: 10.1108/compel-04-2017-0166.

Shobhit Kumar Garg, and Balwinder Singh, “A Novel Design of an Efficient Low Power Phase Frequency Detector for Delay Locked Loop,”, IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016), pp. 1-4, 2016.

K. Khare, N. Khare, P. Deshpande, and V. Kulhade, "Phase frequency detector of delay locked loop at high frequency," Proceedings of IEEE International Conference in Semiconduc-tor Electronics, (ICSE), pp.113-116, June 2008.

J. A. Galan, A. J. López-Martín, R. G. Carvajal, J. Ramírez-Angulo, and C. Rubia-Marcos, “Super class-AB OTAs with adaptive biasing and dynamic output current scaling,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 449-457, 2007.

S. M. Anisheh, H. Abbasizadeh, H. Shamsi, C. Dadkhah, and K.-Y. Lee, “98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process,” IEEE Access, vol. 7. Institute of Electrical and Electronics Engineers (IEEE), pp. 17772–17779, 2019. doi: 10.1109/access.2019.2896089.




DOI: https://doi.org/10.33180/InfMIDEM2026.102

Refbacks

  • There are currently no refbacks.


Copyright (c) 2026 Hamid Gholipour Golroudbari, Hadi Dehbovid, Reza Yousefi, Seyed Saleh Ghoreishi Amiri, Habib Adarang

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.