Nano CMOS Charge Pump for Readerless RFID PLL

Md Torikul Islam Badal, Mamun Bin Ibne Reaz, Mohammad Arif Sobhan Bhuiyan


Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLLs) are among the most crucial functional blocks in the Readerless RFID where the PLL performance greatly depend on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. In order to overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintain the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V and the core occupies 17 x 59.5 μm2. The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performances.


Charge pump; CMOS; Current mismatch; PLL; RFID

Full Text:



Jiang X., Yu X., Moez K., Elliott D. High-Efficiency Charge Pumps for Low-Power On-Chip Applications, IEEE journal of Solid State Circuit, 2018, 65(3): 1143 – 1153.

Boyu Shen and Matthew L. Johnston, 2018. Zero Reversion Loss, 2018. High-Efficiency Charge Pump for Wide Output Current Load Range, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 04 May, 20-25.

Ali E, Hangmann C, Hedayat C, Haddad F, Rahajandraibe W, Hilleringmann U. Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL, IEEE Transactions on Circuits and Systems I, Regular Papers, 2016, 63(3), pp. 347-358.

Minhad K N, Reaz M B I, Ali S H M. Investigating phase detectors. IEEE Microwave Magazine, 2015. 16(11), pp. 56-78.

Fazeel H M S, Raghavan L, Srinivasaraman C, Jain M. Reduction of current mismatch in PLL charge pump, Proceeding of the IEEE Computer Society Annual Symposium on VLSI, 2009. pp. 7-12.

Estebsari M, Gholami M, Ghahramanpour M. A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops, Circuits System and Signal Processing, 2017, 36(9), pp. 3514–3526.

Chen Y, Mak P I, Zhou Y. Self-tracking charge pump for fast-locking PLL, Electronics letters, 2010, 46(11), pp. 755-757.

Jeong C H, Kim K Y, Kwon C K, Kim H, Kim S W. Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops, IET Circuits, Devices, Systems, 2013, 7(6), pp. 313-318.

Choi Y S, Han D H. Gain-boosting charge pump for current matching in phase-locked loop, IEEE Transactions on Circuits and Systems II, Express Briefs, 2006, 53(10), pp. 1022-1025.

Zaziabl A. Low power 1 GHz charge pump phase-locked loop in 0.18 µm CMOS process, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems-(MIXDES), 2010, pp. 277-282.

Kailuke C, Agrawal P, Kshirsagar R. Design of phase frequency detector and charge pump for low voltage high frequency PLL, IEEE International Conference On Electronic Systems, Signal Processing and Computing Technologies (ICESC), 2014. pp. 74-78.

Liu P, Sun P, Jung J, Heo D. PLL charge pump with adaptive body-bias compensation for minimum current variation, Electronics letters, 2012, 48(1), pp. 16-18.

Park J, Kim N, Won D, Choi H. High performance two-stage charge-pump for spur reduction in CMOS PLL, Proceeding of the 11th IEEE International Multi-Conference on Signal, System and Device (SSD), 2014, pp. 1-7.

Tsitouras A, Plessas F, Birbas M, Kalivas G. A 1V CMOS programmable accurate charge pump with wide output voltage range, Microelectronics Journal, 2011, 42(9), pp. 1082-1089.

Gupta J A, Sangal A, Verma H. High speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology, Proceedings of the IEEE world Congress on Information and Communication Technologies (WICT), 2011, pp. 346-349.

Paemel M V. Analysis of a charge-pump PLL, a new model. IEEE Transactions on communications, 1994, 42(7), pp. 2490-2498.

Cheng S, Tong H, Martinez J S, Karsilayan A I. Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching, IEEE Transactions on Circuits and Systems II, Express Briefs, 2006, 53(9), pp. 843-47.

Rhee W. Design of high-performance CMOS charge pumps in phase-locked loops, Proceeding of the 1999 IEEE International Symposium on Circuits and Systems (Florida, USA), 1999, pp. 545-548.

Larsson P. A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability, IEEE Journal of Solid-State Circuits, 1999, 34(12), pp. 1951-60.

Ahola R, Halonen, K. A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer, IEEE Journal of Solid-State Circuits, 2003. 38(1), pp. 138-140.

Lee J S, Keel M S, Lim S I, Kim S. Charge pump with perfect current matching characteristics in phase-locked loops, Electronics Letters, 2000, 36(23), pp. 1907-1908.

Huh H. et al, A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge pump, Proceeding of the IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers. 2004, pp. 100-101.

Zhiqun L, Shuangshuang Z, Ningbing H. Design of a high-performance CMOS charge pump for phase-locked loop synthesizers, Journal of Semiconductors, 2011, 32(7), pp. 075007.

Yoshimura T, Iwade S, Makino H, Matsuda, Y. Analysis of pull-in range limit by charge pump mismatch in a linear phase-locked loop, IEEE Transactions on Circuits and Systems I, Regular Papers, 2013, 60(4), pp. 896-907.

Park J W, Choi H Y, Kim N S. Two-stage feedback-looped charge-pump for spur reduction in CMOS PLL, Analog Integrated Circuits and Signal Processing, 2015, 83(2), pp. 143-148.

Lozada O, Espinosa G. A charge pump with a 0.32% of current mismatch for a high speed PLL, Analog Integrated Circuits and Signal Processing, 2016, 86(2), pp. 321-326.



  • There are currently no refbacks.

Copyright (c) 2015 Informacije MIDEM

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.