CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Ali Rahnamaei


In this article, the design fashion of high-speed 5-2 and 6-2 compressors along with their analysis, has been discussed. With the help of combinational logic consisting of the 4-2 compressor and 3-2 counter structures, a high-performance structure for 6-2 compressor has been obtained which shows significant speed improvement over previous architectures. The optimization is achieved by reducing the carry rippling issue between adjacent compressor blocks. Also, the proposed 6-2 compressor with some modifications will turn into a 5-2 compressor in which latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The delay of proposed 5-2 and 6-2 structures is equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and transistor count of proposed circuits are in reasonable level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of previously reported schemes.


6-2 compressor; 5-2 compressor; multiplier; CMOS; high-speed

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