Hardware Implementation of Chaotic Zigzag Map Based Bitwise Dynamical PRNG on FPGA

Ali Murat GARİPCAN, Ebubekir Erdem

Abstract


In this study, successful real-time implementation of discrete-time chaotic zigzag map as a Random Number Generator on field-programmable gate array (FPGA) environment is presented. For hardware implementation, in addition to ready-use circuit elements defined on 32-bit floating-point numbers, very high-speed integrated circuit hardware description language (VHDL) is used. In the scope of this study, cryptographic critical competencies such as system reliability and randomness quality related to nonlinear dynamic behaviour of zigzag map are examined. H function post - processing technique is used in the system for random numbers with low statistical quality achieved from chaotic system. Also NIST 800-22 standard test technique is used for statistical verification of bit sequences obtained from the generator. In addition to its practical applicability, the results show that the zigzag map can be used as a random number generator for embeded cryptographic applications.

Keywords


FPGA; pseudo-random number generator; chaotic zigzag map; H function post-processing.

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References


S. Ergün, S. Özoğuz, “A chaos-modulated dual oscillator-based truly random number generator”, In 2007 IEEE International Symposium on Circuits and Systems, pp. 2482-2485, 2007, https://doi:10.1109/iscas.2007.378742.

F. Özkaynak “Cryptographically secure random number generator with chaotic additional input”, Nonlinear Dynamics, 78(3): 2015-2020, 2014, https://doi:10.1007/s11071-014-1591-y.

Garipcan, A. M., Erdem, E., “Implementation and performance analysis of true random number generator on FPGA environment by using non-periodic chaotic signals obtained from chaotic maps” Arabian Journal for Science and Engineering, 44(11): 9427-9441, 2019, https://doi:10.1007/s13369-019-04027-x.

D. Lambić, M. Nikolić, “Pseudo-random number generator based on discrete-space chaotic map”, Nonlinear Dynamics, 90(1): 223–232, 2017, https://doi:10.1007/s11071-017-3656-1.

Koyuncu, İ., Tuna, M., Pehlivan, İ., Fidan, C. B., & Alçın, M., “Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator” Analog Integrated Circuits and Signal Processing, 102(2): 445-456, 2020, https://doi.org/10.1007/s10470-019-01568-x.

H. Nejati, A. Beirami, W. H. Ali, “Discrete-time chaotic-map truly random number generators: design, implementation, and variability analysis of the zigzag map” Analog Integrated Circuits and Signal Processing, 73(1): 363-374, 2012, https://doi:10.1007/s10470-012-9893-9.

İ. Çiçek, A.E. Pusane, G. Dündar, “ Random number generation using field programmable analog array implementation of logistic map” In 2013 21st Signal Processing and Communications Applications Conference (SIU), pp. 1-4, 2013, https://doi:10.1109/siu.2013.6531560.

M. Garcia-Bosque, A. Pérez-Resa, C. Sánchez-Azqueta, C. Aldea, S. Celma, “Chaos-based bitwise dynamical pseudorandom number generator on FPGA” IEEE Transactions on Instrumentation and Measurement, 68(1): 291-293, 2018, https://doi:10.1109/tim.2018.2877859.

İ. Cicek, A. E. Pusane, G. Dundar, “ A novel design method for discrete time chaos based true random number generators” INTEGRATION, the VLSI journal, 47(1): 38-47, 2014, https://doi:10.1016/j.vlsi.2013.06.003.

H. Khanzadi, M. Eshghi, S. E. Borujeni, “Design and FPGA implementation of a pseudo random bit generator using chaotic maps” IETE Journal of Research, 59(1): 63-73, 2013, https://doi:10.4103/0377-2063.110633.

Garipcan, A. M., Erdem, E., “Implementation of a Digital TRNG Using Jitter Based Multiple Entropy Source on FPGA” Informacije MIDEM, 49(2): 79-90, (2019)

İ. Koyuncu, A.T. Özcerit, “The design and realization of a new high speed FPGA-based chaotic true random number generator”, Computers & Electrical Engineering, 58: 203-214, 2017, https://doi:10.1016/j.compeleceng.2016.07.005.

M. O. Meranza-Castillón, M. A. Murillo-Escobar, R. M. López-Gutiérrez, C. Cruz-Hernández, “Pseudorandom number generator based on enhanced Hénon map and its implementation” AEU-International Journal of Electronics and Communications, 107: 239-251, 2019, https://doi:10.1016/j.aeue.2019.05.028.

L.G. De la Fraga, E. Torres-Pérez, E. Tlelo-Cuautle, C. Mancillas-López, “ Hardware implementation of pseudo-random number generators based on chaotic maps” Nonlinear Dynamics, 90(3): 1661–1670, 2017, https://doi:10.1007/s11071-017-3755-z.

Dichtl, M. “Bad and Good Ways of Post-processing Biased Physical Random Numbers” In International Workshop on Fast Software Encryption (pp. 137-152). Springer, Berlin, Heidelberg, https://doi:10.1007/978-3-540-74619-5_9.

E. Torres-Perez, L. G. De la Fraga, E. Tlelo-Cuautle, W. D. Leon-Salas, “On the FPGA implementation of random number generators from chaotic maps” In 2017 IEEE XXIV international conference on electronics, electrical engineering and computing (INTERCON), pp. 1-4, 2017, https://doi:10.1109/intercon.2017.8079696

Garipcan, A. M., Erdem, E., “A TRNG using chaotic entropy pool as a post-processing technique: analysis, design and FPGA implementation” Analog Integrated Circuits and Signal Processing, pp. 1-20, 2020, https://doi.org/10.1007/s10470-020-01605-0.

Tuncer, T., “The implementation of chaos-based PUF designs in field programmable gate array. Nonlinear dynamics”, 86(2), 975-986, 2016, https:// doi:10.1007/s11071-016-2938-3.

E. Avaroğlu, T. Tuncer, A.B. Özer, B. Ergen, M. Türk, “A novel chaos-based post-processing for TRNG”, Nonlinear Dynamics, 81(1-2), 189-199, 2015, https://doi:10.1007/s11071-015-1981-9.




DOI: https://doi.org/10.33180/InfMIDEM2020.402

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