Memristor based Majority Logic Adders for Error Resilient Image Processing Applications
Abstract
Approximate Computing (AC) enables energy-efficient and high-performance computation for error-resilient applications such as data analytics, image processing, and multimedia. With the growing demand for low-power, high-density storage in Artificial Intelligence and Machine learning applications, researchers are exploring emerging technologies like FinFETs, memristors, Carbon Nano Tube FET(CNTFET), and Quantum-dot Cellular Automata (QCA) to mitigate the constraints of CMOS scaling. This paper proposes an efficient majority logic design using hybrid memristor-CMOS technology for low-power arithmetic applications. A power-efficient 1-bit adder, comprising three majority gates and one inverter, is designed and compared with existing memristor-based adders. Three Approximate Adder designs such as MAA1, MAA2, and MAA3 are implemented in 8-bit fully approximate ripple carry structure and 8-bit error-tolerant ripple carry structure, integrating four approximate and four accurate adders. Circuit performance, including power and delay, is analyzed using Cadence Virtuoso, where MAA1 achieves the lowest Power-Delay Product (PDP) in both structures. Image quality metrics, assessed using MATLAB with 8-bit pixel depth images, indicate that MAA3 attains the highest Peak Signal-to-Noise Ratio (PSNR) in the fully approximate structure. Error analysis using Verilog coding shows that the proposed MAA2 design achieves a 24.12% error rate reduction in the error-tolerant structure compared to its fully approximate counterpart, demonstrating its efficiency in balancing accuracy and power consumption.
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DOI: https://doi.org/10.33180/InfMIDEM2025.404
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