Subthreshold Modeling of Triple Material Gate-All-Around Junctionless Tunnel FET with Germanium and High-K Gate Dielectric Material

Lakshmi Priya

Abstract


In this paper, a subthreshold analytical model for Triple Material Gate-All-Around (TMGAA) Junctionless Tunnel FET (JLTFET) with Germanium and High-K gate dielectric material is developed. Various performance metrics like Transconductance-to-Drain Current ratio, Subthreshold leakage current, and Subthreshold Swing are derived to model the subthreshold behavior of the device. The gate structure incorporates the effect of Germanium (Ge) and High-K gate dielectric material (Titanium Oxide) to combat the adverse effects imposed by the short channel. The subthreshold characteristics of Ge based JLTFET is compared with Silicon (Si) based TFET with SiO2 as gate dielectric. The results concede that the developed model is highly immune to hot carrier damage because of high transconductance-to-drain current ratio of 50V-1, minimal leakage current and subthreshold swing less than 40mV/dec. The results of the proposed analytical model are validated using 2-D Sentaurus TCAD device simulator.


Keywords


Germanium;Junctionless; High-K gate dielectric; Hot Carrier Reliability; Tunnel FET; Transconductance-to-Drain Current ratio; Subthreshold Current; Subthreshold Swing.

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References


S. E. Thompson and S. Parthasarathy, “Moore’s law: the futureof Si microelectronics,” Materials Today, vol. 9, no. 6, pp. 20–25, 2006

G. Venkateshwar Reddy and M. Jagadesh Kumar , “ A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET- Two Dimensional Analytical Modeling and Simulation”, IEEE Transaction on Nanotechnology, Vol. 4, pp.260-268, /March 2005.

Chen, Z., Xiao, Y., Tang, M., Xiong, Y., Huang, J., Li, J., Gu, X., Zhou, Y., ”Surface-potential-based drain current model for longchannel junctionless double gateMOSFETs”, IEEE Trans. Electron Devices 59(12), 3292–3298 (2012)

Baruah, R.K., Paily, R.P.,”A dual-material gate junctionless transistor with high- k spacer for enhanced analog performance”, IEEE Trans. Electron Devices 61(1), 123–128 (2014)

Long,W.,Ou, H.,Kuo, J.M.,Chin, K.K., ”Dualmaterial gate (DMG) field effect transistor”, IEEE Trans. Electron Devices 46, 865–870 (1999)

Ashutosh Kumar Agrawal, P. N. V. R. Koutilya,M. Jagadesh Kumar, ”A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor”, J Comput Electron, DOI 10.1007/s10825-015-0710-4 (2015)

Kumar, M.J.,Chaudhary,A.,”Two-dimensional analytical modeling of fully depleted DMGSOIMOSFET and evidence for diminished SCEs”, IEEE Trans. Electron Devices 51(4), 569–574 (2004)

T. Skotnicki, C. Fenouillet-Beranger, C. Gallon et al., “Innovative materials, devices, and CMOS technologies for low-power mobile multimedia,” IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 96–130, 2008.

J. Robertson, “High dielectric constant oxides€”, Eur. Phys. J. Appl. Phys. 28, 265–291 (2004)

Toh E H, Wang G H, Chan L, et al., “Device design and scalability of a double-gate tunnelling field-effect transistor with silicon–germanium source”, Jpn J ApplPhys,2008, 47(4): 2593

Kim S H, Kam H, Hu C, et al,.” Germanium-source tunnel field effect transistors with record high ION/IOFF”, IEEE VLSI Symp on VLSI Technology, 2009: 178

K.Boucart and A.Ioneacu, “Double gate tunnel FETs with high-k gate dielectric”, IEEE Trans.,Electron Devices,54 (7) (2007) 1725-1733, Jul.

Ren,C., Yu,H., Kang,J.,Wang, X.,Ma,H.,Yeo,Y.,Chan,D.,LLi, M.,Kwong,D,”A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate. IEEE Electron Device Lett. 25(8), 580-582 (2004).

M. A. Abdi, F. Djeffal, Z. Dibi, and D. Arar, “A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs,” J. Comput. Electron., vol. 10, no. 1/2, pp. 179–185, Jun. 2011.

T. K. Chiang, “A new compact subthreshold behavior model for Dual- Material Surrounding Gate (DMSG) MOSFETs,” Solid State Electron., vol. 53, no. 5, pp. 490–496, May 2009.

V. Kilchytska, A. Neve, L. Vancaillie, D. Levacq, S. Adriaensen, H. van Meer, K. D. Meyer, C. Raynaud, M. Dehan, J. P. Raskin, and D. Flandre, “Influence of device engineering on the analog and RF performances of SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 577–588, Mar. 2003.

Y. Pratap, P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, "An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering", Microelectronics J., vol. 45, no. 4, pp. 408–415, 2014.

P. Suveetha Dhanaselvam, N. B. Balamurugan, and V. N. Ramakrishnan,”A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs”, Microelectronics J., vol. 44, no. 12, pp. 1159–1164, 2013.

R. Gautam, M. Saxena, R. S. Gupta, and M. Gupta, "Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance", Electron Devices, IEEE Trans., vol. 60, no. 6, pp. 1820–1827, 2013.

T.-K. Chiang and J. J. Liou, "An analytical subthreshold current/swing model for junctionless cylindrical nanowire FETs (JLCNFETs) ", Facta Universitatis Series: Electronics and Energetics, vol. 26, no. 3, pp. 157–173, 2013.

S.Theodore Chandra, Dr.N.B.Balamurugan, G.Lakshmi Priya and S.Manikandan, “Subthreshold behavior of AlInSb/InSb high electron mobility transistors”, Chin. Phys. B, vol.24, No. 7, pp. 076105-076105-5, 2015.


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