Implementation of a Digital TRNG Using Jitter Based Multiple Entropy Source on FPGA

Abstract

In this study, hardware implementation and evaluation of a true random number generator (TRNG) were presented. For the implementation, Field Programmable Gate Array (FPGA) hardware in which numerical processes based on an algorithmic basis are carried out, was used. In the system, free oscillation ring oscillators with similar structures were used as a noise source, and true randomness was obtained by sampling the jitter signals formed on the oscillators. However, the most critical cryptographic disadvantage of jitter-based TRNGs is the statistical inadequacy of the system. At this point, in contrast to existing designs, entropy sources derived from the subsets of ring oscillators were used in the sampling and post-processing stage. The statistical quality of the system was improved by using true random numbers/inputs obtained from these entropy sources in the sampling and post-processing stage. With sampling and post-processing inputs, the use of complex post-processing techniques that limit the output bit rate of the generator in the system was not required. Thus, a high-performance TRNG model, of which resource consumption is reduced in terms of hardware and which is simple and easily adaptable in terms of applicability was obtained. The statistical validation of the TRNG, which was tested in a total of 6 different scenarios for two separate ring oscillator architectures and three different operating frequencies, was performed with the NIST 800-22 test package.