Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

Sriram Sundar Subramanian, Mahendran Gandhi

Abstract


Abstract: As the demand for computational capabilities continues to grow, the design and optimization of arithmetic circuits have more crucial in modern digital systems. The efficient operations of these arithmetic circuits heavily depend on the performance of fundamental modules such as Full Adders (FA). In addition to addressing typical challenges, designing full adder circuits using alternative logic offers unique advantages that are vital for the developing landscape of digital system. This paper presents two FAs based an alternative structure using double pass-transistor logic (DPL). The FA cells were designed and implemented in Cadence EDA platform on gptk 45nm CMOS technology. The proposed circuits performance were compared with other conventional logic and few hybrid adders. In comparison with other logics, various type of simulation results indicate that the proposed FA-2 exhibits improved performance in terms of average power, average delay, and average power-delay product (PDP). Our proposed FA-2 shows performance improvement over conventional CMOS for Power, Delay, and PDP, with values of 3.304%, 69.017%, and 74.602%, respectively. Full adders were simulated under different supply voltages and process corners to measure the reliability and robustness. Noise tolerances of full adder circuits were calculated using Average Noise Threshold Energy (ANTE) methodology. Also, we implemented an 8-bit Ripple Carry Adder and verified the effective operation in large bit size words. Various simulations and analysis were carried out by Cadence Spectre tool.


Keywords


Full Adder, Alternative Logic, Multiplexer, Double Pass Transistor, Low Power

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References


Mehedi Hasan, Abdul Hasib Siddique, Abdal Hoque Mondol, Mainul Hossain, Hasan U. Zaman and Sharnali Islam, “Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis”, SN Applied Sciences 3:644 (2021). https://doi.org/10.1007/s42452-021-04640-2.

M. Aguirre-Hernandez and M. Linares-Aranda, "CMOS Full-Adders for Energy-Efficient Arithmetic Applications," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 718-721, April 2011.

doi: 10.1109/TVLSI.2009.2038166

Neil H. E. Weste and David Money Harris, “CMOS VLSI Design- A Circuits and Systems Perspective”, Fourth Edition, Pearson Publication, 2010.

Thiruvengadam Rajagopal and Arvind Chakrapani, “A Novel High-Performance Hybrid Full Adder for VLSI Circuits”, Circuits, Systems, and Signal Processing 40, 5718–5732 (2021).

https://doi.org/10.1007/s00034-021-01725-6.

Mingyan Zhang, Jiangmin Gu and Chip-Hong Chang, "A novel hybrid pass logic with static CMOS output drive full-adder cell," 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, pp. V-317 – V-320, 2003.

doi: 10.1109/ISCAS.2003.1206266

B. C. Devnath and S. N. Biswas, "An Energy-Efficient Full-Adder Design Using Pass-Transistor Logic," 2019 2nd International Conference on Innovation in Engineering and Technology (ICIET), Dhaka, Bangladesh, 2019, pp. 1-6.

doi: 10.1109/ICIET48527.2019.9290550.

M. Rahimi and M.B. Ghaznavi-Ghoushchi, "A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency", Microelectronics Journal, vol. 113, 2021.

https://doi.org/10.1016/j.mejo.2021.105086.

Nan Zhuang and Haomin Wu, “A New Design of the CMOS Full Adder” IEEE Journal of Solid-State Circuits, vol. 27, no. 5, May 1992.

doi: 10.1109/4.133177.

Zarin Tabassum, Meem Shahrin, Aniqa Ibnat, Tawfiq Amin, “Comparative Analysis and Simulation of Different CMOS Full Adders Using Cadence in 90 nm Technology” 2018 3rd International Conference for Convergence in Technology (I2CT), Pune, India, Apr 06-08, 2018.

doi: 10.1109/I2CT.2018.8529482.

Fang Lu and Henry Samueli, “A High-Speed CMOS Full-Adder Cell using a New Circuit Design Technique – Adaptively-Biased Pseudo-Nmos Logic”, IEEE International Symposium on Circuits and Systems, pp. 563-565, May 1990.

doi: 10.1109/ISCAS.1990.112118.

Reto Zimmermann and Wolfgang Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, July 1997.

doi: 10.1109/4.597298.

K.T. Lau, “Digital IC functions with Differential Cascode Voltage Switch Circuits”, IEEE Transactions on Consumer Electronics, vol 34, Issue: 4, November 1988.

doi: 10.1109/30.9901.

Lixin Gao, “High Performance Complementary Pass Transistor Logic Full Adder”, 2011 International Conference on Electronic & Mechanical Engineering and Information Technology, pp. 4306 – 4309, August, 2011. doi: 10.1109/EMEIT.2011.6023114

Fang-shi Lai and Wei Hwang, “Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems”, IEEE Journal of Solid-State Circuits, vol 32, Issue:4, pp. 563 – 573, April 1997.

doi: 10.1109/4.563678.

M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki and Y. Nakagome, “A 1.5-ns 32-b CMOS ALU in double pass-transistor logic”, IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1145-1151, November 1993.

doi: 10.1109/4.245595

A. Parameswar, H. Hara and T. Sakurai, “A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications”, IEEE Journal of Solid-State Circuits,vol 31, Issue: 6, pp. 804 – 809, June 1996.

doi: 10.1109/4.509866.

T. Bhagyalaxmi, S. Rajendar, S. Srinivas, “Power-Aware Alternative Adder Cell Structure Using Swing Restored Complementary Pass Transistor Logic at 45nm Technology”, 2nd International Conference on Nanomaterials and Technologies (CNT 2014), Procedia Materials Science , vol 10, 789 – 792, 2015.

https://doi.org/10.1016/j.mspro.2015.06.021

Minkyu Song, Geunsoon Kang, Seongwon Kim, Euro Joe and Bongsoon Kang, “Design of a low power 7-bit serial counter with Energy economized pass-transistor logic (EEPL)”, lCECS ‘96, Proceedings of Third International Conference on Electronics, Circuits and Systems, October 1996.

doi: 10.1109/ICECS.1996.584563.

Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung, “A Novel Multiplexer-Based Low-Power Full Adder”, IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 51, no. 7, pp. 345-348, July 2004.

doi: 10.1109/TCSII.2004.831429.

Pankaj Kumar and Rajender Kumar Sharma, “Low voltage high performance hybrid full adder”, Engineering Science and Technology, an International Journal , vol 19, Issue 1, Pages 559-565, March 2016. https://doi.org/10.1016/j.jestch.2015.10.001

Hamed Naseri and Somayeh Timarchi, “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol: 26, Issue: 8, pp. 1481 – 1493, August 2018. doi: 10.1109/TVLSI.2018.2820999.

Mehedi Hasan, Md. Shahbaz Hussain, Mainul Hossain, Mohd. Hasan, Hasan U. Zaman and Sharnali Islam, “A high-speed and scalable XOR-XNOR-based hybrid full adder design”, Computers & Electrical Engineering, vol. 93, July 2021. https://doi.org/10.1016/j.compeleceng.2021.107200.

Jyoti Kandpal, Abhishek Tomar and Mayur Agarwal, “Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications”, Microelectronics Journal, vol 115, September 2021.

https://doi.org/10.1016/j.mejo.2021.105205.

S. Sharmila Devi and V. Bhanumathi, “Design of reversible logic based full adder in current-mode logic circuits”, Microprocessors and Microsystems”, vol 76, July 2020.

https://doi.org/10.1016/j.micpro.2020.103100.

Azeem Mohammed Abdul , N.V.S.S. Prasanna, K.V. Harish Kumar and K. Banu Teja, “14-T hybrid full adder design and its implementation for high-performance arithmetic applications”, Materials Today: Proceedings, vol 69, Part 2, Pages 454-458, 2022. https://doi.org/10.1016/j.matpr.2022.09.137.

Parisa Rahimi, Myasar Tabany and Seyedali Pourmoafi “A Novel Low Power and High Speed 9-Transistors Dynamic Full-Adder Cell Simulation and Design”, 2023 IEEE Symposium on Computers and Communications (ISCC), page 1287-1292, 2023.

doi: 10.1109/ISCC58397.2023.10217831.

M. Aguirre and M. Linares, “An alternative logic approach to implement high-speed low-power full adder cells,” in Proc. SBCCI, Florianopolis, Brazil, pp. 166–171, Sep. 2005. doi: 10.1109/SBCCI.2005.4286851.

Rajesh S . Parthasarathy and Ramalingam Sridhar, “Double Pass-Transistor Logic for High Performance Wave Pipeline Circuits”, Proceedings Eleventh International Conference on VLSI Design, Chennai, India, 04-07 January 1998.

doi: 10.1109/ICVD.1998.646655.

Uming Ko, Poras T. Balsara, and Wai Lee, “Low-Power Design Techniques for High-Performance CMOS Adders,” IEEE Transactions on VLSI Systems, Vol. 3, No. 2, June 1995.

doi: 10.1109/92.386232.

G. A. Katopis, "Delta-I noise specification for a high-performance computing machine," in Proceedings of the IEEE, vol. 73, no. 9, pp. 1405-1415, Sept. 1985.

doi: 10.1109/PROC.1985.13301.

Sriram Sundar S, Mahendran G, "CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications", Integration, Volume 95, 2024. https://doi.org/10.1016/j.vlsi.2023.102132.




DOI: https://doi.org/10.33180/InfMIDEM2024.303

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