Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributive Arithmetic for 2D DTCWT Computation on FPGA

Poornima B, Sumathi A, Cyril Prasanna Raj Premkumar


This paper presents customized Systolic Array Architecture (SAA) design of Dual Tree Complex Wavelet (DTCWT) sub band computation based on multiplexed Distributive Arithmetic Algorithm (DAA). The proposed architecture is memory efficient and operates at frequencies greater than 300 MHz in decomposing 256 x 256 input images. Three architectures such as reduced order structure, multiplexed DA structure and zero pad structure are designed and evaluated for its performances for DTCWT computation minimizing arithmetic operations with improved latency. The proposed design is modeled in Verilog HDL and is implemented on Spartan-6 and Virtex-5 FPGA considering Xilinx ISE FPGA design flow. The latency of proposed architectures is evaluated to be 15 clock cycles and throughput is estimated to be 4 outputs for every 5 clock cycles. The SAA architecture occupies less than 12% of FPGA resources and consumes less than 10 mW of power on FPGA platform.


Memory efficient; FPGA, high speed; Systolic Array; Distributive Arithmetic

Full Text:



Nick Kingsbury “Image processing with complex wavelets” Philosophical Transactions of the Royal Society London A, 357 no. 1760:2543–2560, 1999

Ioana Adam “Complex Wavelet Transform: application to denoising” PhD thesis, Politehnica University of Timisoara

Ivan W. Selesnick, Richard G. Baraniuk, and Nick G. Kingsbury “The Dual-Tree Complex Wavelet Transform” IEEE Signal Processing Magazine, 22(6):123–151, 2005.

S. C. Olhede and Georgios Metikas “The HyperanalyticWavelet Transform” Technical report, Imperial College Statistics Section, 2006.

N.G. Kingsbury “Complex wavelets for shift invariant analysis and filtering of signals” Journal of Applied and Computational Harmonic Analysis, 10, no.3:234–253, 2001

N G Kingsbury “The dual-tree complex wavelet transform: a new efficient tool for image restoration and enhancement” In Proc. European Signal Processing Conference, EUSIPCO 98, Rhodes, pages 319–322, 1998

Ivan W. Selesnick “The Double-Density Dual-Tree DWT” IEEE Transactions on Signal Processing, 52, No. 5:1304–1314, 2004.

M. Salagean and I.Firoiu “Anomaly Detection on Network Traffic Based on Analytical Discrete Wavelet Transform” In Proceedings of International Conference Communications 2010, Bucharest, 2010

Das, A. Hazra, and S. Banerjee, “An Efficient Architecture for 3-D Discrete Wavelet Transform,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 20, NO. 2, pp. 286-296, Feb. 2010.

Lan, X., Zheng, N., Liu, Y. “Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform” IEEE Trans. Consum. Electron., 51, (2), pp. 379–385, 2005

S Barua, JE Carletta, KA Kotteri, AE Bell, “An efficient architecture for lifting-based two-dimensional discrete wavelet transforms” J. Integration, VLSI J. 38(3), 341–352, 2005

Martina, M., Masera, G. “Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture” IEEE Trans. Circuits Syst. II: Express Briefs, 54, (9), pp. 770–774, 2007

Seo, Y.H., Kim, D.W. “VLSI architecture of line-based lifting wavelet transform for motion JPEG 2000” IEEE J. Solid-State Circuits., 42, pp. 431–440, 2007

H Varshney, M Hasan, S Jain, “Energy efficient novel architectures for the lifting-based discrete wavelet transform” IET Image Process. 1(3), 305–310, 2007

M. Jiang and D. Crookes, “Area-efficient high-speed 3D DW processor architecture” Electron. Lett., vol. 43, no. 9, pp. 502–503, Apr. 2007

W. Zhang, Z. Jiang, Z. Gao, and Y. Liu, “An efficient VLSI architecture for lifting-based discrete wavelet transform” IEEE Trans. Circuits Syst.II, vol. 59, no. 3, pp. 158–162, 2012

K. Mohanty, A. Mahajan, and P. K. Meher, “Area- and power efficient architecture for high-throughput implementation of lifting 2-D DWT” IEEE Trans. Circuits Syst. II, vol. 59, no. 7, pp. 434–438, 2012

SM Aziz, DM Pham, “Efficient parallel architecture for multi-level forward discrete wavelet transform processors” J. Comp. Elect. Eng. 38, 1325–1335, 2012

Anand D Darji, Shailendra Singh Kushwah, Shabbir N Merchant and Arun N Chandorkar, “High-performance hardware architectures for multi-level lifting-based discrete wavelet transform” EURASIP Journal on Image and Video Processing, 2014

Anand Darji, Arun R., Shabbir Noman Merchant, Arun Chandorkar, “Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform” IET Computers & Digital Techniques, Vol. 9, Iss. 2, pp. 113–123, 2015

B.K.N.Srinivasarao and Indrajit Chakrabarti, “High Speed VLSI Architecture for 3-D Discrete Wavelet Transform”, Sep 2015 downloaded from

Hongda Wang and Chiu-Sing Choy, “Systolic Array based VLSI architecture for high throughput 2-D DWT” IEEE International Conference on Electron devices and solid state circuits (EDSSC), pp: 100-103, 2016

Chakraborty, D. Chakraborty, and A. Banerjee, “A Multiplier less VLSI Architecture of Modified Lifting Based 1D/2D DWT using Speculative Adder”, International Conference on Communication and Signal Processing, April 6-8, India, 2017

Rakesh Biswas, Siddarth Reddy Malreddy, and Swapna Banerjee, “A High-Precision Low-Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform” IEEE transactions on circuits and systems for video technology, vol. 28, no. 9, September 2018, pp: 2386-2396, 2018

S. S. Divakara, Sudarshan Patilkulkarni, Cyril Prasanna Raj, “High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT” International Journal of Image and Graphics Vol. 18, No. 1, 2018



  • There are currently no refbacks.

Copyright (c) 2015 Informacije MIDEM

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.