Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

Zhifeng Zhao, Tianyu Yu, Peng Si, Kai Zhang, Weifeng Lyu


In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio (ION/IOFF) and steeper subthreshold swing (SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.


Negative-capacitance double-gate junctionless field-effect transistor; additional source-drain doping; on/off current ratio; subthreshold swing; drain induced barrier lowering

Full Text:



E. Ko, J. Shin and C. Shin, "Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors." Nano Convergence, Vol. 5, no. 2, pp. 1-9, 2018.

C. Lee, A. Afzalian, N. D. Akhavan, R. Yan, L. Ferain and J. Colinge, "Junctionless multigate field-effect transistor." Appl. Phys. Lett, Vol. 94, no. 5, pp. 053511, 2009.

J. Colinge, C. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. Kelleher, B. McCarthy and R. Murphy, "Nanowire transistors without junctions." Nat. Nanotechnol, Vol. 5, no. 3, pp. 225-229, 2010.

S. Salahuddin, S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices." Nano Lett, Vol. 8, no. 2, pp. 405-410, 2008.

A. M. Ionescu, "Negative capacitance gives a positive boost." Nat. Nanotechnol, Vol. 13, no. 1, pp. 7-8, 2018.

V. Kumari, A. Kumar, M. Saxena and M. Gupta, "Study of Gaussian Doped Double Gate Junction-Less (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior." Superlattices Microstruct, Vol. 113, pp. 57-70, 2017.

C. Jiang, R. Liang, J. Wang and J. Xu, "Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate di-electric." Solid-State Electron, Vol. 126, pp. 130-135, 2016.

N. M. Hossain, S. Quader, A. B. Siddik and M. I. B. Chowdhury, "TCAD based performance analysis of junctionless cylindrical double gate all around FET up to 5nm technology node." in 20th Inter-national Conference of Computer and Information Technology (ICCIT), 2017.

H. Y. Yu, C. Ren, Y. Yeo, J. F. Kang, X. P. Wang, H. H. H. Ma, M. F. Li, D. S. H. Chan and D. L. Kwong, "Fermi pinning-induced thermal instabil-ity of metal-gate work functions." IEEE Electron Device Lett, Vol. 25, no. 5, pp. 337-339, 2004.

C. Lin, A. I. Khan, S. Salahuddin and C. Hu, "Ef-fects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics." IEEE Trans. Electron Devices, Vol. 63, no. 5, pp. 2197-2199, 2016.

Y. Lin, H. Agarwal, M. Kao, J. Zhou, Y. Liao, A. Dasgupta, P. Kushwaha, S. Salahuddin and C. Hu, "Spacer Engineering in Negative Capacitance FinFETs." IEEE Electron Device Lett, Vol. 40, no. 6, pp. 1009-1012, 2019.

T. Yu, W. Lü, Z. Zhao, P. Si and K. Zhang, "Effect of different capacitance matching on negative capacitance FDSOI transistors." Microelectron. J, Vol. 98, pp. 104730, 2020.

Y. Choi, Y. Hong and C. Shin, "Device design guideline for junctionless gate-all-around nan-owire negative-capacitance FET with HfO2-based ferroelectric gate stack." Semicond. Sci. Technol, Vol. 35, no. 1, pp. 015011, 2020.

H. Mehta, H. Kaur, "Impact of Gaussian Doping Profile and Negative Capacitance Effect on Dou-ble-Gate Junctionless Transistors (DGJLTs)." IEEE Trans. Electron Devices, Vol. 65, no. 7, pp. 2699-2706, 2018.

C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin and C. Hu, "Low power negative capacitance FETs for future quantum-well body technology." in International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013, pp. 1-2.

D. Moon, S. Choi, J. P. Duarte and Y. Choi, "Inves-tigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Sub-strate." IEEE Trans. Electron Devices, Vol. 60, no. 4, pp. 1355-1360, 2013.

C. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akha-van, P. Razavi, J. Colinge, "Performance estima-tion of junctionless multigate transistors." Solid-State Electron, Vol. 54, no. 2, pp. 97-103, 2010.

L. Tu, X. Wang, J. Wang, X. Meng and J. Chu, "Ferroelectric Negative Capacitance Field Effect Transistor." Adv. Electron. Mater, Vol. 4, no. 11, pp. 1800231, 2018.

S. Gupta, M. Steiner, A. Aziz, V. Narayanan, S. Datta and S. K. Gupta, "Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic." IEEE Trans. Electron Devices, Vol. 64, no. 8, pp. 3092-3100, 2017.

H. Amrouch, G. Pahwa, A. D. Gaidhane, J. Henkel and Y. S. Chauhan, "Negative Capacitance Tran-sistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance." IEEE Access, Vol. 6, pp.52754-52765, 2018.

Guide, Sentaurus Device User, and G. Version. “Synopsys.” Inc., Sep (2017).

M. Kao, Y. Lin, H. Agarwal, Y. Liao, P. Kushwaha, A. Dasgupta, S. Salahuddin and C. Hu, "Optimi-zation of NCFET by Matching Dielectric and Fer-roelectric Nonuniformly Along the Channel." IEEE Electron Device Lett, Vol. 40, no. 5, pp. 822-825, 2019.

M. H. Park, Y. H. Lee, H. J. Kim, Y. J. Kim, T. Moon, K. D. Kim, J. Müller, A. Kersch, U. Schroeder, T. Mikolajick and C. S. Hwang, "Fer-roelectricity and Antiferroelectricity of Doped Thin HfO2‐Based Films." Adv. Mater, Vol. 27, no. 11, pp. 1811-1831, 2015.

C. W. Yeung, A. I. Khan, S. Salahuddin and C. Hu, "Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs." in Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2013.

B. Awadhiya, P. N. Kondekar, A. D. Meshram, "Effect of Ferroelectric Thickness Variation in Un-doped HfO 2 -Based Negative-Capacitance Field-Effect Transistor." J. Electron. Mater, Vol. 48, no. 10, pp. 6762-6770, 2019.



  • There are currently no refbacks.

Copyright (c) 2020 Zhifeng Zhao, Tianyu Yu, Peng Si, Kai Zhang, Weifeng Lyu

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.